SST32HF202 查看數據表（PDF） - Silicon Storage Technology
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SST32HF202 Datasheet PDF : 26 Pages
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
ADDRESSES AMSS-0
BES#
OE#
UBS#, LBS#
DQ15-0
TRCS
TAAS
TBES
TBLZS
TOES
TOLZS
TBYES
TBYLZS
TOHS
TBHZS
TOHZS
TBYHZS
DATA VALID
Note: WE# remains High (VIH) for the Read cycle
AMSS = Most Significant SRAM Address
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
557 ILL F02.0
ADDRESSES AMSS-0
WE#
BES#
TWCS
TASTS
TWPS
TBWS
TAWS
TWRS
UBS#, LBS#
DQ15-8, DQ7-0
TBYWS
TODWS
NOTE 2
TDSS
TOEWS
TDHS
VALID DATA IN
NOTE 2
557 ILL F03.1
FIGURE
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.
If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2001 Silicon Storage Technology, Inc.
11
S71209-00-000 9/01 557
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