SST39LF200A 查看數據表（PDF） - Microchip Technology
零件编号
产品描述 (功能)
生产厂家
SST39LF200A Datasheet PDF : 37 Pages
| |||
A Microchip Technology Company
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Device Operation
Data Sheet
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39LF200A/400A/800A and SST39VF200A/400A/800A is controlled by
CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE#
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure
5).
Word-Program Operation
The SST39LF200A/400A/800A and SST39VF200A/400A/800A are programmed on a word-by-word
basis. Before programming, the sector where the word exists must be fully erased. The Program oper-
ation is accomplished in three steps. The first step is the three-byte load sequence for Software Data
Protection. The second step is to load word address and word data. During the Word-Program opera-
tion, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the
internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever
occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 6 and 7
for WE# and CE# controlled Program operation timing diagrams and Figure 18 for flowcharts. During
the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks. Any commands issued during the internal
Program operation are ignored.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39LF200A/400A/800A and SST39VF200A/400A/800A offers both Sec-
tor-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord.
The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is ini-
tiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector
address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte com-
mand sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The
sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Tog-
gle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sec-
tor- or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1” state. This is useful when the entire device
must be quickly erased.
©2011 Silicon Storage Technology, Inc.
7
DS25001A
03/11
Share Link: 