ST10F163 查看數據表（PDF） - STMicroelectronics
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ST10F163 Datasheet PDF : 58 Pages
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ST10F163
16-BIT MCU WITH 128KBYTE FLASH MEMORY
s HIGH PERFORMANCE CPU
– HIGH PERFORMANCE 16-BIT CPU WITH
4-STAGE PIPELINE
– 80ns INSTRUCTION CYCLE TIME @ 25MHz CPU
CLOCK
– 400ns MULTIPLICATION (16 × 16 BITS)
– 800ns DIVISION (32 / 16 BIT)
– ENHANCED BOOLEAN BIT MANIPULATION FA-
CILITIES
– ADDITIONAL INSTRUCTIONS TO SUPPORT HLL
AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
s MEMORY ORGANIZATION
– UP TO 16 MBYTES LINEAR ADDRESS SPACE
FOR CODE AND DATA (1MBYTE WITH SSP
USED)
– 1 KBYTES ON-CHIP RAM
– 128 KBYTES ON-CHIP FLASH MEMORY
– 4 INDEPENDENTLY ERASABLE BANKS OF
FLASH
s FAST AND FLEXIBLE BUS
– PROGRAMMABLE EBC
– 8-BIT OR 16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTER-
NAL ADDRESS/DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD AND HOLD-ACKNOWLEDGE BUS ARBI-
TRATION SUPPORT
s ON-CHIP BOOTSTRAP LOADER
s FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG
s INTERRUPT
– 8-CHANNEL INTERRUPT-DRIVEN SINGLE-CY-
CLE DATA TRANSFER FACILITIES VIA PERIPH-
ERAL EVENT CONTROLLER (PEC)
– 16-PRIORITY-LEVEL INTERRUPT SYSTEM
WITH 20 SOURCES, SAMPLE-RATE DOWN TO
40ns
s TIMERS
– TWO GENERAL PURPOSE TIMER UNITS WITH 5
TIME RS
s CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT
PQFP100 (14 x 14 mm)
(Plastic Quad Flat Pack)
s UP TO 77 GENERAL PURPOSE I/O LINES
s IDLE AND POWER DOWN MODES
s SERIAL CHANNELS
– SYNCHRONOUS/ASYNCHRONOUS
– HIGH-SPEEDSYNCHRONOUS SERIAL PORTSSP
s DEVELOPMENT SUPPORT
– C-COMPILERS, MACRO-ASSEMBLER PACKAG-
ES, EMULATORS, EVALUATION BOARDS,
HLL-DEBUGGERS, SIMULATORS, LOGIC ANA-
LYZER DISASSEMBLERS, PROGRAMMING
BOARDS
s PACKAGE
– 100-PIN THIN QUAD FLAT PACK (TQFP)
CPU
PEC
Interrupt Controller
BRG
BRG
P.6 P.5
P.3
P.2
April 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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