28F016XS 查看數據表（PDF） - Intel

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28F016XS

16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY

Intel 

28F016XS FLASH MEMORY

E

address inputs. During read operations, addresses

are latched and accesses are initiated on a rising

CLK edge in conjunction with ADV# low. Both CLK

and ADV# are ignored by the 28F016XS during

command/data write sequences.

The 28F016XS incorporates SmartVoltage

technology, providing VCC operation at both 3.3V

and 5.0V and program and erase capability at

VPP = 12.0V or 5.0V. Operating at VCC = 3.3V, the

28F016XS consumes less than one half the power

consumption at 5.0V VCC, while 5.0V VCC provides

highest read performance capability. VPP operation

at 5.0V eliminates the need for a separate 12.0V

converter, while the VPP = 12.0V option maximizes

program/erase performance. In addition to the

flexible program and erase voltages, the dedicated

VPP gives complete code protection with VPP ≤

VPPLK.

A 3/5# input pin configures the device’s internal

circuitry for optimal 3.3V or 5.0V read/program

operation.

A Command User Interface (CUI) serves as the

system interface between the microprocessor or

microcontroller and the internal memory operation.

Internal Algorithm Automation allows program and

block erase operations to be executed using a Two-

Write command sequence to the CUI in the same

way as the 28F008SA 8-Mbit FlashFile™ memory.

Software locking of memory blocks is an added

feature of the 28F016XS as compared to the

28F008SA. The 28F016XS provides selectable

block locking to protect code or data such as direct-

executable operating systems or application code.

Each block has an associated nonvolatile lock-bit

which determines the lock status of the block. In

addition, the 28F016XS has a master Write Protect

pin (WP#) which prevents any modifications to

memory blocks whose lock-bits are set.

Writing of memory data is performed in either byte

or word increments, typically within 6 µs at 12.0V

VPP, which is a 33% improvement over the

28F008SA. A block erase operation erases one of

the 16 blocks in typically 1.2 sec, independent of

the other blocks.

Each block can be written and erased a minimum of

100,000 cycles. Systems can achieve one million

Block Erase Cycles by providing wear-leveling

algorithms and graceful block retirement. These

techniques have already been employed in many

flash file systems and hard disk drive designs.

All operations are started by a sequence of Write

commands to the device. Three Status Registers

(described in detail later in this datasheet) and a

RY/BY# output pin provide information on the

progress of the requested operation.

The following Status Registers are used to provide

device and WSM operation information to the user:

• A Compatible Status Register (CSR) which is

100% compatible with the 28F008SA FlashFile

memory Status Register. The CSR, when used

alone, provides a straightforward upgrade

capability to the 28F016XS from a 28F008SA-

based design.

• A Global Status Register (GSR) which also

informs the system of overall Write State

Machine (WSM) status.

• 16 Block Status Registers (BSRs) which

provide block-specific status information such

as the block lock-bit status.

The GSR and BSR memory maps for Byte-Wide

and Word-Wide modes are shown in Figures 5

and 6.

The 28F016XS incorporates an open drain RY/BY#

output pin. This feature allows the user to OR-tie

many RY/BY# pins together in a multiple memory

configuration such as a Resident Flash Array.

The 28F016XS also incorporates a dual chip-

enable function with two input pins, CE0# and CE1#.

These pins have exactly the same functionality as

the regular chip-enable pin, CE#, on the 28F008SA.

For minimum chip designs, CE1# may be tied to

ground and system logic may use CE0# as the chip

enable input. The 28F016XS uses the logical

combination of these two signals to enable or

disable the entire chip. Both CE0# and CE1# must

be active low to enable the device. If either one

becomes inactive, the chip will be disabled. This

feature, along with the open drain RY/BY# pin,

allows the system designer to reduce the number of

control pins used in a large array of 16-Mbit

devices.

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