STLC4420A 查看數據表（PDF） - STMicroelectronics

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STLC4420A

Single chip 802.11b/g/a WLAN radio

STMicroelectronics 

STLC4420A

Electrical specifications

Table 2. General electrical specifications (continued)

Parameter

Test condition / comment

BIAS DAC supply

voltage

Tdod

SPI_DOUT delay from transmit

edge of SPI_CLK

SPI_DOUT Tdozh

SPI_DOUT delay before HI-Z state

from rising edge of SPI_CSX

Tdozd

SPI_DOUT delay before driven

from HI-Z state on falling edge of

SPI_CSX

Min.

2.8

0

0

Typ.

Max.

3.15

Units

V

7

ns

ns

10

ns

Table 3. Host interface specifications

Parameter

Test condition / comment

Min.

Typ.

Max. Units

Digital interface specifications

VIH

POWER_UP

Input

VIL

Pull-Down

Host CMOS VIH

Inputs

VIL

Host CMOS

Outputs

VOH

VOL

Input Current

OSC_EN

Input

VOH

VOL

REF_CLK

Input

Input Level

Accuracy

SLEEP_CLK

Input

Frequency

Accuracy

Duty Cycle

PMU Power up control. Active

High.

VIO supply domain

IOH = 0.2mA, VIO supply domain

IOL = 6mA, VIO supply domain

VIO supply domain

IOH <= 2mA

IOL <= 2mA

AC coupled

VIO supply domain

0.8

-

VBATT

V

0

-

0.3

V

-

500

-

K ohms

0.7*VIO

-

VIO + 0.3 V

0

-

0.3*VIO

V

VIO - 0.2 -

VIO

V

0

-

0.6

V

-1.0

-

+1.0

µA

1.4

-

-

V

-

-

0.4

V

500

-

1000 mVpp

-

-

25

ppm

-

32.768

-

kHz

-

-

150

ppm

30

-

70

%

SPI timing specifications (refer to Figure 3)

Tcmin

SPI_CLK Period

20.8

ns

SPI_CLK Tch

SPI_CLK High Time

10.4

ns

Tcl

SPI_CLK Low Time

10.4

ns

Tcssu

SPI_CSX Setup time to first clock

edge

10.4

ns

SPI_CSX

Tcsh

SPI_CSX hold time from last clock

edge

10.4

ns

19/40

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