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VSC7148(2000) 查看數據表(PDF) - Vitesse Semiconductor

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VSC7148 Datasheet PDF : 2 Pages
1 2
VITESSE
SEMICONDUCTOR CORPORATION
Product Brief
VSC7148
16-Port JBOD Loop Chip for
1.0625 Gb/s FC-AL Storage Applications
Features
All the functionality needed to implement a com-
plete daisy-chainable 16-drive 1Gb/s FC-AL JBOD
Subsystem
• Two host ports with two pairs of FibreTimerTM
Clock Recovery Units (CRUs) configurable as
either Repeaters or Retimers
• Sixteen Port Bypass Circuits (PBC) for drive con-
trol
• Sixteen PBC internal Snoop LoopTM for loop diag-
nostics
Applications
• Configurable as either a single 16-drive loop or
two 8-drive loops
• I2C interface for configuration/status/control
• Seamless interface to Enclosure Management
Chipsets such as the Vitesse SSC100/VSC055
for managed JBOD applications
• On-chip terminators selectable as 100/150 ohm
• 3.3V Power Supply, 4.3 W
• 256-pin, 27mm Thermally Enhanced BGA
The VSC7148 contains all the functions needed to implement an entire daisy-chainable 1.0625 Gb/s FC-AL
JBOD Loop for storage systems containing up to sixteen disk drives. This device is typically used in distribut-
ing Fibre Channel signals to an array of disk drives in managed and un-managed arrays. The use of an I2C
Interface allows access to status information and control of configuration through an easily-implemented,
industry-standard, protocol.
The VSC7148 easily interfaces with the SSC100 Enclosure Management Controller to offer unsurpassed
diagnostic capability within the industry (refer to Figure 1). The SSC100 communicates with the VSC7148
through the I2C interface to provide complete loop status, configuration, and diagnostic control to the host. In
this configuration, up to fifteen drives on a single loop may be accessed with a single Fibre Channel connector.
Serial data from the loop enters the FC-AL port of the SSC100 where the data is processed, returned to the loop,
and handed to the VSC7148 for drive communications. In addition, the VSC7148 is the only device on the mar-
ket that supports two loops within a single device. The External Loop may be configured for all Fibre Channel
data traffic while the Snoop Loop may be used for monitoring or isolating specific ports for diagnostics. With
this architecture, a design engineer has the flexibility to offer full Fibre Channel support on the External Loop
IPMI
RS-232
Ethernet
SSSSCC110000
EEnncclolossuurere
MMaannaaggeemmeennt t
CCoonntrtorolllelerr
Host
Port #1
Repeater
Retimer
(4) FibreTimerTM
Circuits
Host
Port #2
Repeater
Retimer
External
Loop
PBC 0
Snoop
Loop
External External External
Loop
Loop
Loop
PBC 1 PBC 2 PBC 3
Snoop
Loop
Snoop
Loop
Snoop
Loop
External
Loop
PBC 15
Snoop
Loop
VSC7148 16-Port JBOD Loop Chip
For diagnostic testing,
the SSC100 initiates
communication with
an individual drive
(e.g. Drive 3) via the
VSC7148 Snoop
LoopTM while all other
drives are fully
accessible to the Fibre
Channel loop.
Figure 1. Managed JBOD Using the VSC7148 and SSC100
Rev. 1.0
5/25/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1

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