TQ8101-C 查看數據表（PDF） - TriQuint Semiconductor
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TQ8101-C Datasheet PDF : 14 Pages
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TQ8101C
Framing
The demultiplexer block (see Figure 2) includes a
frame-detection and recovery block. Regardless of the
state of the OOF input signal, this block takes DXSYNC
high for one period of DXCK whenever it detects a
pattern of three “A1” bytes followed by three “A2”
bytes.
Frame recovery is initiated by the rising edge of the
OOF input signal. The recovery process involves a
search for a bit rotation that satisfies the three-“A1”–
three-“A2” byte pattern specified for SONET/SDH. Once
the pattern is found, DXSYNC goes high and the bit
rotation is synchronized to the correct byte boundaries.
No further byte boundary adjustments are made,
regardless of “A1”-“A2” indication, unless they have
been preceded by an OOF rising edge.
PLL Clock Synthesis
The PLL utilizes a monolithic voltage-controlled
oscillator with a typical tuning constant of 50 to 100
MHz per volt on the TUNE input. This configuration
provides jitter performance superior to other
technologies. In a typical SONET/SDH application the
TUNE input and charge pump output IOUT are
connected and tied to VEE through a 600-ohm resistor
and 0.68-µF capacitor.
Loopback
The TQ8101C features four loopback modes: normal
(pass-through), equipment loopback, split loopback,
and facility loopback. Loopback modes are controlled
by pins CNTL(3:0). Note␣ that the loopback mode does
not affect the latched selection of clock modes and
rates. Note that the RXCK input is␣ directly connected to
the TXCK output in most loopback modes (see below).
Figure 5. TQ8101C Loopback Modes
Normal
RXDT
RXCK
DXDTIN
DXHSCK
TXDT
TXCK
MXDTOUT
MXHSCK
Equipment Loopback
DXDTIN
DXHSCK
TXDT
TXCK
MXDTOUT
MXHSCK
Split Loopback
RXDT
RXCK
DXDTIN
DXHSCK
TXDT
TXCK
MXDTOUT
MXHSCK
Facility Loopback
RXDT
RXCK
DXDTIN
DXHSCK
TXDT
TXCK
4
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