V29LC51000 查看數據表（PDF） - Mosel Vitelic, Corp

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V29LC51000

512 KILOBIT (65,536 x 8 BIT) 5 VOLT CMOS FLASH MEMORY

Mosel Vitelic, Corp 

MOSEL VITELIC

V29LC51000

Table 2. Command Codes

Command

Sequence

First Bus

Second Bus

Third Bus

Fourth Bus

Program Cycle Program Cycle Program Cycle Program Cycle

Address Data Address Data Address Data Address Data

Fifth Bus

Six Bus

Program Cycle Program Cycle

Address Data Address Data

Read

XXXXH F0H

Read

5555H AAH 2AAAH 55H 5555H F0H RA

RD

Autoselect 5555H AAH 2AAAH 55H 5555H 90H 00H

40H(3)

01H

20H(4)

Byte

Program

5555H AAH 2AAAH 55H 5555H A0H PA

PD(2)

Chip Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Sector Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H PA(1)

30H

NOTES:

1. PA: The address of the memory location to be programmed.

2. PD: The data at the byte address to be programmed.

3. 40H: Manufacturing ID

4. 20H: Device ID

Chip Erase Cycle

The V29LC51000 features a chip-erase

operation. The chip erase operation is initiated by

using a specific six-bus-cycle sequence: two unlock

program cycles, a setup command, two additional

unlock program cycles, and the chip erase

command (see Table 2).

The chip erase operation is performed

sequentially, one sector at a time. When the

automated on chip erase algorithm is requested

with the chip erase command sequence, the device

automatically programs and verifies the entire

memory array for an all zero pattern prior to erasure

The automatic erase begins on the rising edge of

the last WE or CE pulse in the command sequence

and terminates 500ms later.

Hardware Data Protection

VCC Sense Protection: the program operation is

inhibited when VCC is less than 2.5V.

Noise Protection: a CE or WE pulse of less than

5ns will not initiate a program cycle.

Program Inhibit Protection: holding any one of

OE LOW, CE HIGH or WE HIGH inhibits a program

cycle.

V29LC51000 Rev. 0.4 October 2000

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