VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7216-01
Multi-Gigabit Interconnect Chip
AC Specifications
Figure 13: Transmit Input Timing Waveforms with TMODE = 000
REFCLK
(DUAL=0)
REFCLK
(DUAL=1)
Internal Clock
(from PLL)
Tn(7:0)
C/Dn
Valid
WSENn
T1
T2
Valid
T1
T2
Valid
Figure 14: Transmit Input Timing Waveforms with TMODE = 10X
TBCn
(or TBCA)
Internal Clock
(from PLL)
Tn(7:0)
C/Dn
Valid
WSENn
T1
T2
Valid
T1
T2
Valid
Table 10: Transmit Input AC Characteristics with TMODE = 000 or TMODE = 10X
Parameters
T1
T2
Description
Input setup time to the rising
edge of REFCLK or TBCn
Input hold time after the rising
edge of REFCLK or TBCn
Min
Max Units
Conditions
1.5
—
ns Measured between the valid data
level of the input and the 1.4V point
1.0
—
ns of REFCLK or TBCn
G52352-0, Rev 3.2
05/05/01
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