VSC7216-01 查看數據表（PDF） - Vitesse Semiconductor

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VSC7216-01

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7216-01

Multi-Gigabit Interconnect Chip

Serializer

The 10-bit output from the encoder (or from the encoder input register if ENDEC is LOW) is fed into a

multiplexer which serializes the parallel data using the synthesized transmit clock. The least significant bit of

the 10B data is transmitted first. Each channel has both primary and redundant serial output ports, PTXn and

RTXn respectively, which consist of differential PECL output buffers operating at either 10 or 20 times the

REFCLK rate. The primary and redundant transmitter outputs are separately controllable on each channel. The

primary PECL outputs PTXn are enabled when the PTXENn input is HIGH, and the redundant PECL outputs

RTXn are enabled when the RTXENn input is HIGH. When a PECL output is disabled, the associated output

buffers do not consume power and the attached pins are un-driven. The PECL outputs do not require external

resistors.

Receiver Functional Description

Serial Data Source

Each receive channel has both primary and redundant serial input ports, PRXn and RRXn, respectively,

which consist of differential PECL input buffers. Each channel also has a control input, RXP/Rn, used to select

either the primary or redundant serial input as the data source for that channel. When RXP/RC is HIGH, the C

channel serial data source is PRXC. When LBENn(1:0)=10, the channel’s transmitter is looped back and

becomes the serial data source regardless of the state of RXP/Rn (see Table 5).

Table 5: Serial Data Source Selection

LBENn(1:0)

≠10

≠10

=10

RXP/Rn

0

1

X

Serial Data Source

RRXn

PRXn

LBTXn

Loopback fromTransmitters

Signal Detection

Each channel’s primary and redundant PECL input buffers have an associated signal detect output,

PSDETn and RSDETn. All eight outputs are available for continuous monitoring of both the selected and non-

selected input. Each signal detect output is asserted HIGH when transitions are detected on the associated PECL

input and the signal amplitude exceeds 200mV under nominal operating conditions. A LOW indicates that

either no transitions are detected or the signal amplitude is below 100mV under nominal operating conditions.

The signal detect outputs are considered undefined when the signal amplitude is in the 100mV to 200mV range.

The signal detect circuitry behaves like a re-triggerable one-shot that is triggered by signal transitions, and

whose time-out interval ranges from 40 to 80 bit times. The transition density is not checked to make sure that it

G52352-0, Rev 3.2

05/05/01

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