VSC7216-01 查看數據表（PDF） - Vitesse Semiconductor
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VSC7216-01 Datasheet PDF : 38 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Multi-Gigabit Interconnect Chip
Multi-Gigabit Interconnect Chip
Preliminary Data Sheet
VSCV7S2C1672-0116
corresponds to a valid Fibre Channel data stream. The PSDETn and RSDETn output timing is identical to the
low-speed receiver outputs, as selected by RMODE(1:0). See Table 6.
Receiver Equalization
Incoming data on the PRX/RRX inputs typically contains a substantial amount of Inter Symbol Interference
(ISI) or deterministic jitter which reduces the ability of the receiver to recover data without errors. An equalizer
has been added to each of the receiver’s input buffers in order to compensate for this deterministic jitter. This
circuit has been designed to effectively reduce the ISI commonly found in copper cables or backplane traces due
to low frequencies traveling faster than high frequencies as a result of the skin effect. The equalizer boosts high
frequency edge response in order to reduce the adverse effects of ISI.
Clock and Data Recovery
At the receiver, each channel contains an independent Clock Recovery Unit (CRU) which accepts the
selected serial input source, extracts the high-speed clock and retimes the data. Each CRU automatically locks
on data and if the data is not present, will automatically lock to the REFCLK. This maintains a very well-
behaved recovered clock, RCLKn/RCLKNn which does not contain any slivers and will operate at a frequency
of the REFCLK reference ±200 ppm. The use of an external Lock-to-Reference pin is not needed.
The Clock Recovery Unit must perform bit synchronization which occurs when the CRU locks onto and
properly samples the incoming serial data as described in the previous paragraph. When the CRU is not locked
onto the serial data, the 10-bit data out of the decoder is invalid which results in numerous 8B/10B decoding
errors or disparity errors. When the link is disturbed (e.g., the cable is disconnected or the serial data source is
switched), the CRU will require a certain amount of time to lock onto data which is specified in the AC Timing
Characteristics for “Data Acquisition Lock Time.”
Deserializer and Character Alignment
The retimed serial data stream is converted into 10-bit characters by the deserializer. A special 7-bit
“Comma” pattern (‘0011111xxx’ or ‘1100000xxx’) is recognized by the receiver and allows it to identify the
10-bit character boundary. Note that this pattern is found in three special characters, K28.1, K28.5 and K28.7,
however, K28.5 is chosen as the unique IDLE character. Only K28.1 and K28.5 should be used in normal
operation. The K28.7 character should be reserved for test and characterization use.
Character alignment occurs when the deserializer synchronizes the 10-bit character framing boundary to a
“Comma” pattern in the incoming serial data stream. If the receiver identifies a “Comma” pattern in the
incoming data stream which is misaligned to the current framing boundary the receiver will re-synchronize the
recovered data in order to align the data to the new “Comma” pattern. Re-synchronization ensures that the
“Comma” character is output on the internal 10-bit bus so that bits 0 through 9 equal ‘0011111xxx’ or
‘1100000xxx’. If the “Comma” pattern is aligned with the current framing boundary, re-synchronization will
not change the current alignment. Re-synchronization is always enabled and cannot be turned off when ENDEC
is HIGH. After character re-synchronization the VSC7216-01 ensures that within a link, the 8-bit data sent to
the transmitting VSC7216-01 will be recovered by the receiving VSC7216-01 in the same bit locations as the
transmitter (i.e., Tn(7:0) = Rn(7:0)). When ENDEC is LOW, “Comma” detection and alignment are enabled
only if KCHAR is HIGH.
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© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52352-0, Rev 3.2
05/05/01
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