WED2CG472512V15D2 查看數據表（PDF） - White Electronic Designs Corporation
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WED2CG472512V15D2
White Electronic Designs Corporation
WED2CG472512V15D2 Datasheet PDF : 10 Pages
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White Electronic Designs WED2CG472512V-D2
ADVANCED
SYNC BURST – TRUTH TABLE
Operation
E1# E2# E3# E4# ADSP# ADSC# ADV# GW# G# CK
DQ Addr. Used
Deselected Cycle, Power Down; Bank 1 H X * *
X
L
X
X
X L-H High-Z None
Deselected Cycle, Power Down; Bank 2 X H * *
X
L
X
X
X L-H High-Z None
Read Cycle, Begin Burst; Bank 1
L H **
L
X
X
X
L L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L H **
L
X
X
X
H L-H High-Z External
Read Cycle, Begin Burst, Bank 2
H L **
L
X
X
X
L L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H L **
L
X
X
X
H L-H High-Z External
Write Cycle, Begin Burst; Bank 1
L H **
H
L
X
L
X L-H
D
External
Write Cycle, Begin Burst; Bank 2
H L **
H
L
X
L
X L-H
D
External
Read Cycle, Begin Burst; Bank 1
L H **
H
L
X
H
L L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L H **
H
L
X
H
H L-H High-Z External
Read Cycle, Begin Burst; Bank 2
H L **
H
L
X
H
L L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H L **
H
L
X
H
H L-H High-Z External
Read Cycle, Continue Burst; Bank 1
X H **
X
H
L
H
L L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X H **
X
H
L
H
H L-H High-Z Next
Read Cycle, Continue Burst; Bank 2
H X **
X
H
L
H
L L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H X **
X
H
L
H
H L-H High-Z Next
Read Cycle, Continue Burst; Bank 1
H H **
X
H
L
H
L L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H H **
X
H
L
H
H L-H High-Z Next
Read Cycle, Continue Burst; Bank 2
H H **
X
H
L
H
L L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H H **
X
H
L
H
H L-H High-Z Next
Write Cycle, Continue Burst; Bank 1
X H **
H
H
L
L
X L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H H **
X
H
L
L
X L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H X **
H
H
L
L
X L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H H **
X
H
L
L
X L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X H **
H
H
H
H
L L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X H **
H
H
H
H
H L-H High-Z Current
Read Cycle, Suspend Burst; Bank 2
H X **
H
H
H
H
L L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H X **
H
H
H
H
H L-H High-Z Current
Read Cycle, Suspend Burst; Bank 1
H H **
X
H
H
H
L L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H H **
X
H
H
H
H L-H High-Z Current
Read Cycle, Suspend Burst; Bank 2
H H **
X
H
H
H
L L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H H **
X
H
H
H
H L-H High-Z Current
Write Cycle, Suspend Burst; Bank 1
X H **
H
H
H
L
X L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H H **
X
H
H
L
X L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H X **
H
H
H
L
X L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H H **
X
H
H
L
X L-H
D
Current
Note A: All truth Table Functions Repeat for Bank 3 (E3#) and Bank 4 (E4#).
Operation
Synchronous Write - Bank 1
Synchronous Read - Bank 1
Synchronous Write - Bank 2
Synchronous Read - Bank 2
Synchronous Write - Bank 3
Synchronous Read - Bank 3
Synchronous Write - Bank 4
Synchronous Read - Bank 4
Snooze Mode
SYNCHRONOUS ONLY – TRUTH TABLE
E1#
E2#
E3#
E4# GW#
G#
ZZ
L
H
H
H
L
H
L
L
H
H
H
H
L
L
H
L
H
H
L
H
L
H
L
H
H
H
L
L
H
H
L
H
L
H
L
H
H
L
H
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
L
L
X
X
X
X
X
X
H
CK
DQ
High-Z
High-Z
High-Z
High-Z
X
High-Z
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Aug. 2002
Rev. B
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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