WED2DL32512V40BC 查看數據表（PDF） - White Electronic Designs Corporation
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WED2DL32512V40BC Datasheet PDF : 9 Pages
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WED2DL32512V
AC CHARACTERISTICS
Parameter
Clock
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
Output Times
Clock to output valid
Clock to output invalid (2)
Clock to output on Low-Z (2,3,4)
Clock to output in High-Z (2,3,4)
OE to output valid (5)
OE to output in Low-Z (2,3,4)
OE to output in High Z (2,3,4)
Setup Times
Address (6,7)
Address status (ADSC) (6,7)
Write signals (BWa-BWd, BWE) (6,7)
Data-in (6,7)
Chip enables (CE) (6,7)
Hold Times
Address (6,7)
Address status (ADSC) (6,7)
Write Signals (BWa-BWd, BWE) (6,7)
Data-in (6,7)
Chip Enables (CE) (6,7)
Symbol
200MHz
Min
Max
166MHz
Min
Max
150MHz
Min
Max
133MHz
Min
Max
Units
tKC
5.0
6.0
6.6
7.5
ns
tKF
200
166
150
133
MHz
tKH
2.0
2.4
2.6
2.6
ns
tKL
2.0
2.4
2.6
2.6
ns
tKQ
2.5
3.5
3.8
4.0
ns
tKQX
1.5
1.25
1.25
1.5
ns
tKQLZ
0
0
0
0
ns
tKQHZ
3.0
3.5
3.8
4.0
ns
tOEQ
2.5
3.5
3.8
4.0
ns
tOELZ
0
0
0
0
ns
tOEHZ
2.5
3.5
3.8
4.0
ns
tAS
1.5
1.5
1.5
1.5
ns
tADSS
1.5
1.5
1.5
1.5
ns
tWS
1.5
1.5
1.5
1.5
ns
tDS
1.5
1.5
1.5
1.5
ns
tCES
1.5
1.5
1.5
1.5
ns
tAH
0.5
0.5
0.5
0.5
ns
tADSH
0.5
0.5
0.5
0.5
ns
tWH
0.5
0.5
0.5
0.5
ns
tDH
0.5
0.5
0.5
0.5
ns
tCEH
0.5
0.5
0.5
0.5
ns
NOTES:
1. Test conditions as specified with the output loading as shown in Figure 1 for 3.3V 1/0 and Figure 3 for 2.5V 1/0 unless otherwise noted.
2. This parameter is measured with output load as shown in Figure 2 for 3.3V 1/0 and Figure 4 for 2.5V 1/0.
3. This parameter is sampled.
4. Transition is measured ±500mV from steady state voltage.
5. OE is a “Don’t Care” when a byte write enable is sampled LOW.
6. A WRITE cycle is defined by at least one byte write enable LOW for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC
LOW for the required setup and hold times.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADSC is LOW and chip enabled. All other
synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when ADSC is LOW to remain enabled.
OUTPUT LOADS
Output
ZZ00==505Ω0Ω
50Ω
VtV=t 1=.51V.5fVor 3.3V I/O
Vt = 1.25V for 2.5V I/O
AC Output Load Equivalent
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3.3V I/O
2.5V I/O Unit
VSS to 3.0
VSS to 2.5 V
1
1
ns
1.5
1.25
V
1.5
1.25
V
See figure, at left
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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