WED3EG6418S-D4 查看數據表（PDF） - White Electronic Designs Corporation

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WED3EG6418S-D4

128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLL

White Electronic Designs Corporation 

WED3EG6418S-D4

FINAL

IDD SPECIFICATIONS AND TEST CONDITIONS

(Recommended operating conditions, tA = 0 to 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V)

Parameter

Symbol Conditions

DDR333@CL=2.5

Max

One device bank; Active = Precharge;

tRC=tRC(MIN); tCK=tCK

Operating Current

IDD0 (MIN); DQ, DM and DQS inputs changing

840

once per clock cycle; Address and control

inputs changing once every two cycles.

One device banks; Active-Read-Precharge;

Operating Current

IDD1

Burst = 2; tRC=tRC(MIN); tCK=tCK

(MIN); lOUT=0mA; Address and control inputs

1040

changing once per clock cycle.

Precharge Power-

Down Standby Current

IDD2P

All device bank idle; Power-down mode;

tCK=tCK(MIN); CKE=(low)

24

CS# = High; All device banks idle;

Idle Standby Current

IDD2F

tCK=tCK(MIN); CKE = high; Address and other

control inputs changing once per clock cycle.

200

VIN = VREF for DQ, DQS and DM.

Active Power-Down

Standby Current

IDD3P

One device bank active; Power-down mode;

tCK(MIN); CKE=(low)

280

CS# = High; CKE = High; One device

bank; Active-Precharge; tRC=tRAS(MAX);

Active Standby Current

IDD3N

tCK=tCK(MIN); DQ, DM and DQS inputs

changing twice per clock cycle; Address and

495

other control inputs changing once per clock

cycle

Burst = 2; Reads; Continous burst; Once

Operating Current

IDD4R

device bank active; Address and control

inputs changing once per clock cycle;

1280

tCK=tCK(MIN); IOUT=0mA

Burst=2; Writes; Continous burst; Once

device bank active; Address and control

Operating Current

IDD4W inputs changing once per clock cycle;

1216

tCK=tCK(MIN); DQ,DM and DQS inputs

changing twice per clock cycle.

Auto Refresh Current

IDD5

tRC=tRC(MIN)

1520

Self Refresh Current

IDD6 CKE £ 0.2V

16

Four bank interleaving Reads (BL=4)

with auto precharge with tRC=tRC(MIN);

Operating Current

IDD7A tCK=tCK(MIN); Address and control input

2640

change only during Active Read or Write

commands.

* Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap.

DDR266@CL=2, 2.5

Max

760

960

24

180

280

440

1140

1040

1440

16

2400

DDR200@CL=2

Max

680

880

24

160

225

360

960

815

1315

16

1920

Units

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

mA

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Oct. 2002

Rev. # 0

5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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