WM8141 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8141 Datasheet PDF : 31 Pages
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WM8141
Production Data
ANALOGUE CHARACTERISTICS (3.3V OPERATION)
Test Conditions
AVDD = DVDD1 = DVDD2 = 2.97V to 3.63V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 8MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
CONDITIONS
Overall System Specification Including CDS, PGA, OFFSET and ADC Functions.
Full-scale input voltage range
Max Gain
(see Note 1)
Min Gain
Input signal limits (see Note 2)
VIN
0
Full-scale transition error
Gain = 0dB;
PGA[7:0] = 4B(hex)
Zero-scale transition error
Gain = 0dB;
PGA[7:0] = 4B(hex)
Differential non-linearity
DNL
Integral non-linearity
INL
Channel to channel gain matching
References
Upper reference voltage
VRT
1.625
Lower reference voltage
VRB
0.900
Input return bias voltage
VRX
0.60
Diff. reference voltage (VRT-VRB)
VRTB
0.65
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
RLCDAC resolution
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCSTEP
VRLCSTEP
VRLCBOT
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
RLCDAC output voltage at
code F(hex), RLCDACRNG = 0
VRLCTOP
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
Offset DAC
Resolution
Differential non-linearity
DNL
Integral non-linearity
INL
Step size
Output voltage
Code 00(hex)
Code FF(hex)
Programmable Gain Amplifier
Resolution
Gain
TYP
MAX
UNIT
0.2
2.04
20
20
0.5
2
1
1.725
0.975
0.65
0.75
1
140
5
2
<0.1
4
0.16
0.09
0.25
0.2
2.75
1.7
AVDD
Vp-p
Vp-p
V
mV
mV
LSB
LSB
%
1.825
V
1.050
V
0.70
V
0.85
V
Ω
Ω
mA
Ω
µA
bits
V/step
V/step
V
V
V
V
8
0.1
0.25
1.02
-130
+130
8
208
283 − PGA[7 : 0]
bits
LSB
LSB
mV/step
mV
mV
bits
V/V
Max gain, each channel
Min gain, each channel
Gain error, each channel
GMAX
GMIN
7.4
V/V
0.74
V/V
1
%
Notes: 1. Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
WOLFSON MICROELECTRONICS LTD
PD Rev 3.0 October 2000
6
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