WM9701 查看數據表（PDF） - Wolfson Microelectronics plc
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WM9701 Datasheet PDF : 24 Pages
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WM9701A
Production Data
SLOT #
0
1
2
3
4
5
6
7
8
9
10 11 12
SYNC
OUTGOING
STREAMS
INCOMING
STREAMS
TAG PHASE
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
PCM
RIGHT
OPT
MDM CDC
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
PCM
RIGHT
OPT
MDM CDC
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
DATA PHASE
Figure 7 AC’97 Standard Bi-directional Audio Frame
SYNC
BIT_CLK
TAG PHASE
12.288MHz
81.4nS
DATA PHASE
20.8µS (48kHz)
SDATA_OUT OUT
VALID
FRAME
SLOT(1)
SLOT(2)
SLOT(12) ’0’ ’0’ ’0’ 19
0
END OF PREVIOUS
AUDIO FRAME
TIME SLOT ’VALID’ BITS
(’1’ = TIME SLOT CONTAINS
VALID PCM DATA)
SLOT (1)
19
0
SLOT (2)
19
0
SLOT (3)
19
0
SLOT (12)
Figure 8 AC-link Audio Output Frame
The data streams currently defined by the AC’97 specification include:
PCM playback - 2 output slots
PCM record data - 2 input slots
Control 2 output slots
Status 2 input slots
Optional modem line Codec output - 1
output slot
Optional modem line Codec input - 1
input slot
Optional dedicated microphone input -
1 input slot
2 channel composite PCM output stream
2 channel composite PCM input stream
Control register write port
Control register read port
Modem line Codec DAC input stream
(Not supported by WM9701A)
Modem line Codec ADC output stream
(Not supported by WM9701A)
Dedicated microphone input stream in support of
stereo AEC, and/or other voice applications.
(Not supported by WM9701A)
Synchronisation of all AC-link data transactions is signalled by the WM9701A controller. WM9701A
drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with a
synchronisation signal to construct audio frames.
SYNC fixed at 48 kHz, is derived by dividing down the serial clock (BIT_CLK). BIT_CLK, fixed at
12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming
time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-
link data, (WM9701A for outgoing data and the AC’97 controller for incoming data), samples each
serial bit on the falling edges of BIT_CLK.
The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid
tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0
indicates that the corresponding time slot within the current audio frame has been assigned to a data
stream, and contains valid data. If a slot is “tagged” invalid, it is the responsibility of the source of the
data, (WM9701A for the input stream, AC’97 controller for the output stream); to stuff all bit positions
with 0s during that slot’s active time.
WOLFSON MICROELECTRONICS LTD.
PD Rev 3.2 January 2001
10
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