28C256 查看數據表（PDF） - Xicor -> Intersil

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28C256

32K x 8 Bit 5 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

X28C256

THE TOGGLE BIT I/O6

Figure 4. Toggle Bit Bus Sequence

LAST

WE WRITE

CE

OE

I/O6

VOH

*

VOL

* Beginning and ending state of I/O6 will vary.

Figure 5. Toggle Bit Software Flow

LAST WRITE

LOAD ACCUM

FROM ADDR n

HIGH Z

*

X28C256

READY

3855 FHD F14

The Toggle Bit can eliminate the software housekeeping

chore of saving and fetching the last address and data

written to a device in order to implement DATA Polling.

This can be especially helpful in an array comprised of

multiple X28C256 memories that is frequently updated.

The timing diagram in Figure 4 illustrates the sequence

of events on the bus. The software flow diagram in

Figure 5 illustrates a method for polling the Toggle Bit.

COMPARE

ACCUM WITH

ADDR n

COMPARE

NO

OK?

YES

X28C256

READY

3855 FHD F15

5

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