28C256 查看數據表（PDF） - Xicor -> Intersil

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28C256

32K x 8 Bit 5 Volt, Byte Alterable E2PROM

Xicor -> Intersil 

X28C256

HARDWARE DATA PROTECTION

The X28C256 provides three hardware features (com-

patible with X28C64) that protect nonvolatile data from

inadvertent writes.

• Noise Protection—A WE pulse typically less than

20ns will not initiate a write cycle.

• Default VCC Sense—All write functions are inhibited

when VCC is ≤3.5V typically.

• Write Inhibit—Holding either OE LOW, WE HIGH,

or CE HIGH will prevent an inadvertent write cycle

during power-up and power-down, maintaining data

integrity.

SOFTWARE DATA PROTECTION

The X28C256 offers a software controlled data protec-

tion feature. The X28C256 is shipped from Xicor with the

software data protection NOT ENABLED; that is, the

device will be in the standard operating mode. In this

mode data should be protected during power-up/-down

operations through the use of external circuits. The host

would then have open read and write access of the

device once VCC was stable.

The X28C256 can be automatically protected during

power-up and power-down without the need for external

circuits by employing the software data protection fea-

ture. The internal software data protection circuit is

enabled after the first write operation utilizing the soft-

ware algorithm. This circuit is nonvolatile and will remain

set for the life of the device unless the reset command

is issued.

Once the software protection is enabled, the X28C256

is also protected from inadvertent and accidental writes

in the powered-up state. That is, the software algorithm

must be issued prior to writing additional data to the

device.

Software Algorithm

Selecting the software data protection mode requires

the host system to precede data write operations by a

series of three write operations to three specific ad-

dresses. Refer to Figure 6 and 7 for the sequence. The

three-byte sequence opens the page write window

enabling the host to write from one to sixty-four bytes of

data.* Once the page load cycle has been completed,

the device will automatically be returned to the data

protected state.

*Note: Once the three-byte sequence is issued it

must be followed by a valid byte or page write

operation.

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