Z53C80 查看數據表（PDF） - Zilog

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Z53C80

SMALL COMPUTER SYSTEM INTERFACE (SCSI)

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READ REGISTERS

Address: 0

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

Figure 27. Current SCSI Data Register

Address: 1

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

Assert Data Bus

Assert /ATN

Assert /SEL

Assert /BSY

Assert /ACK

Lost Arbitration

Arbitration in Progress

Assert /RST

Figure 28. Initiator Command Register

Address: 2

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

Arbitrate

DMA Mode

Monitor /BSY

Enable /EOP Interrupt

Enable Parity Interrupt

Enable Parity Checking

Target Mode

"0"

Figure 29. Mode Register

Z53C80 SCSI

Address: 3

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

Assert I//O

Assert C//D

Assert /MSG

Assert /REQ

"0"

Last Byte Sent

Figure 30. Target Command Register

Address: 4

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

/DBP

/SEL

I//O

C//D

/MSG

/REQ

/BSY

/RST

Figure 31. Current SCSI Bus Status Register

Address: 5

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

/ACK

/ATN

Busy Error

Phase Match

Interrupt Request Active

Parity Error

DMA Request

End of DMA

Figure 32. Bus and Status Register

PS97SCC0200

19

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