AD9364 查看數據表（PDF） - Analog Devices

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AD9364

RF Agile Transceiver

Analog Devices 

Data Sheet

AD9364

Pin No.

F8

F10, G10

F12

G1

G2

G3

G5

G6

G7, G8

G9, H9

G11, H11

H1, J1

H4

H5

H8

H12

J3

J4

J5

J6

J7

J8

J9

J10

J11

Type1 Mnemonic

I/O

P0_D10/TX_D5_N

I

FB_CLK_P, FB_CLK_N

I

VDDD1P3_DIG

I

RX_EXT_LO_IN

O

RX_VCO_LDO_OUT

I

VDDA1P1_RX_VCO

I

EN_AGC

I

ENABLE

O

RX_FRAME_N, RX_FRAME_P

I

TX_FRAME_P, TX_FRAME_N

O

DATA_CLK_P, DATA_CLK_N

I

RXB_P, RXB_N

I

TXNRX

I

SYNC_IN

I/O

P1_D11/RX_D5_P

I

VDD_INTERFACE

I

VDDA1P3_RX_SYNTH

I

SPI_DI

I

SPI_CLK

O

CLK_OUT

I/O

P1_D10/RX_D5_N

I/O

P1_D9/RX_D4_P

I/O

P1_D7/RX_D3_P

I/O

P1_D5/RX_D2_P

I/O

P1_D3/RX_D1_P

Description

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D10, it functions as part of the 12-bit, bidirectional, parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D5_N) can function as part of the LVDS

6-bit Tx differential input bus with internal LVDS termination.

Feedback Clock. These pins receive the FB_CLK signal that clocks in Tx data. In

CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground.

1.3 V Digital Supply Input.

External Receive LO Input. When this pin is unused, tie it to ground.

Receive VCO LDO Output. Connect this pin directly to G3 and a 1 μF bypass

capacitor in series with a 1 Ω resistor to ground.

Receive VCO Supply Input. Connect this pin directly to G2 only.

Manual Control Input for Automatic Gain Control (AGC).

Control Input. This pin moves the device through various operational states.

Receive Digital Data Framing Output Signal. These pins transmit the RX_FRAME

signal that indicates whether the Rx output data is valid. In CMOS mode, use

RX_FRAME_P as the output and leave RX_FRAME_N unconnected.

Transmit Digital Data Framing Input Signal. These pins receive the TX_FRAME

signal that indicates when Tx data is valid. In CMOS mode, use TX_FRAME_P as

the input and tie TX_FRAME_N to ground.

Receive Data Clock Output. These pins transmit the DATA_CLK signal that is used

by the BBP to clock Rx data. In CMOS mode, use DATA_CLK_P as the output and

leave DATA_CLK_N unconnected.

Receive Channel Differential Input B. Alternatively, each pin can be used as a

single-ended input. These inputs experience degraded performance above

3 GHz. Unused pins must be tied to ground.

Enable State Machine Control Signal. This pin controls the data port bus direction.

Logic low selects the Rx direction; logic high selects the Tx direction.

Input to Synchronize Digital Clocks Between Multiple AD9364 Devices. If this pin

is unused, it must be tied to ground.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D11, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D5_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode).

1.3 V Supply Input.

SPI Serial Data Input.

SPI Clock Input.

Output Clock. This pin can be configured to output either a buffered version of the

external input clock, the DCXO, or a divided-down version of the internal ADC_CLK.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D10, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D5_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D9, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D4_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D7, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D3_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D5, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D2_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D3, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D1_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Rev. C | Page 13 of 32

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