AD9364 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD9364

RF Agile Transceiver

Analog Devices 

AD9364

Data Sheet

Pin No.

J12

Type1 Mnemonic

I/O

P1_D1/RX_D0_P

K1, L1

K3

K4

K5

K6

K7

I

RXC_P, RXC_N

I

VDDA1P3_TX_SYNTH

I

VDDA1P3_BB

I

RESETB

I

SPI_ENB

I/O

P1_D8/RX_D4_N

K8

I/O

P1_D6/RX_D3_N

K9

I/O

P1_D4/RX_D2_N

K10

I/O

P1_D2/RX_D1_N

K11

I/O

P1_D0/RX_D0_N

L4

I

L5

I

L6

O

M1, M2

I

M5

I

M7, M8

O

M9, M10

O

M11, M12

I

RBIAS

AUXADC

SPI_DO

RXA_P, RXA_N

TX_MON

TXA_P, TXA_N

TXB_P, TXB_N

XTALP, XTALN

1 I is input, O is output, I/O is input/output, NC is not connected.

Description

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D0_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Receive Channel Differential Input C. Alternatively, each pin can be used as a

single-ended input. These inputs experience degraded performance above

3 GHz. Unused pins must be tied to ground.

1.3 V Supply Input.

1.3 V Supply Input.

Asynchronous Reset. Logic low resets the device.

SPI Enable Input. Set this pin to logic low to enable the SPI bus.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D4_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D3_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D2_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D1_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D0_N) can function as part of the LVDS 6-bit Rx

differential output bus with internal LVDS termination.

Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor

to ground.

Auxiliary ADC Input. If this pin is unused, tie it to ground.

SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode.

Receive Channel Differential Input A. Alternatively, each pin can be used as a

single-ended input. Unused pins must be tied to ground.

Transmit Channel Power Monitor Input. If this pin is unused, tie it to ground.

Transmit Channel Differential Output A. Unused pins must be tied to 1.3 V.

Transmit Channel Differential Output B. Unused pins must be tied to 1.3 V.

Reference Frequency Crystal Connections. When a crystal is used, connect it

between these two pins. When an external clock source is used, connect it to

XTALN and leave XTALP unconnected.

Rev. C | Page 14 of 32

Share Link: