TIMING DIAGRAMS
TIMING DIAGRAMS
IN1,
IN2,
OE
OUTA,
OUTB
50%
tPLH
90%
10%
tPHL
Figure 4. tPLH, tPHL, and tPZH Timing
t VGON
11 V
VDD
VCRES
Figure 6. Charge Pump Timing Diagram
VDDDETON
2.5 V/3.5 V
VDD
0.8 V/
1.5 V
50%
tVDDDET
VDDDETOFF
tVDDDET
90%
IM
0%
(<1.0 µA)
Figure 5. Low-Voltage Detection Timing Diagram
Table 5. Truth Table
INPUT
OE
IN1A
IN2A
L
L
L
H
L
L
L
H
H
X
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
OE terminal is pulled up to VDD with internal resistance.
IN1B
IN2B
L
L
H
H
X
OUT1A
OUT2A
L
H
L
Z
Z
OUTPUT
OUT1B
OUT2B
L
L
H
Z
Z
Analog Integrated Circuit Device Data
Freescale Semiconductor
17529
7