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74LVT273DB,112 查看數據表(PDF) - NXP Semiconductors.

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74LVT273DB,112
NXP
NXP Semiconductors. NXP
74LVT273DB,112 Datasheet PDF : 17 Pages
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NXP Semiconductors
74LVT273
3.3 V octal D-type flip-flop
5. Pinning information
5.1 Pinning
MR 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
74LVT273
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
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Fig 4. Pin configuration for SO20 and (T)SSOP20
terminal 1
index area
74LVT273
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND(1)
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
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Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration for DHVQFN20
5.2 Pin description
Table 2. Pin description
Symbol
Pin
MR
1
Q0 to Q7
2, 5, 6, 9, 12, 15, 16, 19
D0 to D7
3, 4, 7, 8, 13, 14, 17, 18
GND
10
CP
11
VCC
20
Description
master reset input (active LOW)
data output
data input
ground (0 V)
clock pulse input (active on rising edge)
positive supply voltage
74LVT273_3
Product data sheet
Rev. 03 — 10 September 2008
© NXP B.V. 2008. All rights reserved.
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