ADT7467 查看數據表（PDF） - ON Semiconductor

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ADT7467

dbCOOL Remote Thermal Monitor and Fan Controller

ON Semiconductor 

ADT7467

Bit 2 sets the direction for the GPIO: 0 = input, 1 = output.

Bit 3 sets the GPIO polarity: 0 = active low, 1 = active high.

Setting the Functionality of Pin 9

Pin 9 on the ADT7467 has four possible functions:

SMBALERT, THERM, GPIO, and TACH4. The user

chooses the required functionality by setting Bit 0 and Bit 1

of Configuration Register 4 at Address 0x7D.

Table 4. PIN 9 SETTINGS

Bit 1

Bit 0

0

0

0

1

1

0

1

1

Function

TACH4

THERM

SMBALERT

GPIO

Recommended Implementation

Configuring the ADT7467 as in Figure NO TAG allows

the system designer to use the following features:

 Two PWM Outputs for Fan Control of Up to Three

Fans (The Front and Rear Chassis Fans are Connected in

Parallel)

 Three TACH Fan Speed Measurement Inputs

 VCC Measured Internally through Pin 3

 CPU Temperature Measured Using the Remote 1

Temperature Channel

 Ambient Temperature Measured through the Remote 2

Temperature Channel

 Bidirectional THERM Pin. This Feature Allows Intel

Pentium 4 PROCHOT Monitoring and Can Function as

an Overtemperature THERM Output. Alternatively, it

Can be Programmed as an SMBALERT System Interrupt

Output

FRONT

CHASSIS

FAN

ADT7467

TACH2

PWM1

TACH1

CPU FAN

REAR

CHASSIS

FAN

AMBIENT

TEMPERATURE

PWM3

TACH3

D2+

D2−

THERM

D1+

SDA

D1−

SCL

SMBALERT

GND

PROCHOT

ICH

CPU

Figure 14. ADT7467 Implementation

Serial Bus Interface

On PCs and servers, control of the ADT7467 is carried out

using the serial system management bus (SMBus). The

ADT7467 is connected to this bus as a slave device under the

control of a master controller, which is usually (but not

necessarily) the ICH.

The ADT7467 has a fixed 7-bit serial bus address of

0101110 or 0x2E. The read/write bit must be added to get the

8-bit address (01011100 or 0x5C). Data is sent over the serial

bus in sequences of nine clock pulses: eight bits of data

followed by an acknowledge bit from the slave device.

Transitions on the data line must occur during the low period

of the clock signal and remain stable during the high period,

because a low-to-high transition might be interpreted as a

stop signal when the clock is high. The number of data bytes

that can be transmitted over the serial bus in a single read or

write operation is only limited by what the master and slave

devices can handle.

When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10th clock pulse to assert a stop

condition. In read mode, the master device overrides the

acknowledge bit by pulling the data line high during the low

period before the ninth clock pulse. This is known as a no

acknowledge. The master then takes the data line low during

the low period before the 10th clock pulse, and then high

during the 10th clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the

serial bus in one operation. It is not possible to mix a read and

a write in one operation, however, because the type of

operation is determined at the beginning and cannot

subsequently be changed without starting a new operation.

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