X24164PI 查看數據表（PDF） - Xicor -> Intersil
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X24164PI Datasheet PDF : 14 Pages
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X24164
Bus Timing
SCL
SDA IN
tSU:STA
tF
tHIGH
tLOW
tHD:STA tHD:DAT
tSU:DAT
tR
tSU:STO
tAA
tDH
tBUF
SDA OUT
3846 FHD F05
Write Cycle Limits
Symbol
TWR(6)
Parameter
Write Cycle Time
Min.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the X24164
Write Cycle Timing
Typ.(5)
Max.
Units
5
10
ms
3846 PGM T09
bus interface circuits are disabled, SDA is allowed to
remain high, and the device does not respond to its slave
address.
SCL
SDA
8th BIT
WORD n
ACK
STOP
CONDITION
tWR
START
CONDITION
3846 FHD F06
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V).
(6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
120
100
RMIN
=
VCC MAX
IOL MIN
=1.8KΩ
80
RMAX
=
tR
CBUS
60
MAX.
RESISTANCE
40
20 MIN.
RESISTANCE
0
0 20 40 60
80 100 120
BUS CAPACITANCE (pF) 3846 FHD F18
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
11
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