APW7120 查看數據表（PDF） - Anpec Electronics
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APW7120 Datasheet PDF : 22 Pages
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APW7120
Block Diagram
VCC
3VCC
40uA
Regulator
3VCC
67%VREF
118%VREF
Power-On-
Reset
POR
UV
OV
OC
0.4V
Soft-Start
and Fault
Logic
Enable
0.15V
2.5V
Soft-Start
Inhibit
Gate
Control
FB
COMP
PWM
VCC
VREF
0.8V
Gm
Amplifier
Oscillator
FOSC
300kHz
OCSET
BOOT
UGATE
PHASE
LGATE
GND
Application Circuit
VBIAS
+5V /12V
D1
1N 4148
R4
2.2
C1
1uF
B OOT
UGATE
C2
0.1uF
2
5
VC C
8
PH A SE
U 1 OCSET 7
R5
APW 7120
6
FB
4
LGA TE
GND
Shutdown
Q3
2N 7002
R2
1.2k
C3, C4 : 820µF/16V , ESR=25 mΩ
C6, C7 : 1000µF/6.3V, ESR=30 mΩ
Copyright © ANPEC Electronics Corp.
6
Rev. A.5 - Jun., 2008
C5
1uF
Q1
APM2512
L2
1.5uH
Q2
APM2512
R1
1.5k
L1
1uH
C3, C4
820uF x2
VIN
+5/12V
C6, C7
1000uF x2
VOU T
1.8V /15A
C8
R3
0.1uF 200
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