AS3588AQ 查看數據表（PDF） - austriamicrosystems AG
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AS3588AQ Datasheet PDF : 15 Pages
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Data Sheet
Pinout Configuration
AS3588A
OUT PCM3 .
OUT PCM2 .
OUT PCM 1 .
OUT PCM0 .
N.C. .
CLOCK
SYNC
INP PCM7
INP PCM6
INP PCM5
INP PCM4
INP PCM3
INP PCM2
INP PCM1
INP PCM0
VDD
D7
D6
D5
D4
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10 AS3588AP 31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
OUT PCM4
OUT PCM5
OUT PCM6
OUT PCM7
RD
WR
CS1
CS2
RESET
VSS
C/D
A1
S1
A2
S2
DR
D0
D1
D2
D3
CLOCK
SYNCN
INP PCM7
INP PCM6
INP PCM5
INP PCM4
INP PCM3
INP PCM2
INP PCM1
INP PCM0
VDD
1
39
6 AS3588AQ 28
17
NC
WRN
CS1N
CS2N
RESETN
Vss
C/DN
A1
S1
A2
S2
Figure 2: Pinout 40 pin DIP and 44 pin QFP
Pin Description
DIP QFP Type
1 - 4 40 - 43 OP
Symbol
OUTPCM3 to
OUTPCM0
Description
PCM Outputs 3 to 0.
These are open drain outputs for four primary rate PCM output
streams.
5
44, 12,
-
17, 33,
39
6
1
IP
N.C.
Unused Pin
CLOCK
Master Clock Input
This signal is the timing reference for all internal operations. The PCM
bit cell boundaries lie on the alternate rising edges of this clock.
7
2
IP
SYNC
Synchronization Input
This is an edge sensitive input for frame synchronization in the PCM
bit stream with a typical repetition rate of 8 kHz. The rising edge
determines the start of a new frame.
8 - 15 3 - 10 IP
INPPCM7 to PCM Inputs 7 to 0
INPPCM0 These are the inputs for primary rate PCM input streams
16
11 Power
VDD
Positive Supply Voltage
17 - 24 13 - 16, I/O
18 - 21
D7 to DO
Data Bus I/O Port.
These are the bi-directional data pins to the microprocessor interface.
Only 5 bits are used when data is written into AS3588A (D4 to D0)
25
22
OP
DR
Data Ready Output.
This active high signal goes low for signalling purposes
Rev. 3.1
Page 2 of 15
July 1999
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