CS48500 查看數據表（PDF） - Cirrus Logic

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CS48500

32-bit Audio Decoder DSP Family

Cirrus Logic 

CS48500 Data Sheet

32-bit Audio Decoder DSP Family

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

Each version of the CS48500 support a different number of input channels. Refer toTable 2 on page 8 for

more details.

The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz. The

port is capable of accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD is

supported and internally converted to PCM before processing. The DAI also supports a time division

multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line (the total number

possible depends on the ratio of SCLK to LRCLK and the version of chip. For example on the CS48520

only 4 ch of PCM are supported in one line mode and on the CS48560 up to 8 channels are supported.).

The port has two independent slave-only clock domains. Each data input can be independently assigned

T to a clock domain. The sample rate of the input clock domains can be determined automatically by the

DSP, off-loading the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows

F the input data to be sample-rate converted via software.

A 4.2.2 Digital Audio Output Port (DAO)

Each version of the CS48500 support a different number of output channels. Refer toTable 2 on page 8

R for more details.

D DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192

kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a clock

slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can be re-

L configured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with embedded

I clock on a single line).

IA H 4.2.3 Serial Control Port (I2C® or SPI™)

T P The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C® modes.

Master/Slave operation is chosen by mode select pins when the CS48500 comes out of reset. The serial

N L clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be ≤

(Fdclk/2)). The CS48500 serial control port also includes a pin for flow control of the communications

E E interface (#SCP_BSY) and a pin to indicate when the DSP has a message for the host (#SCP_IRQ).

4.2.4 GPIO

ID D Many of the CS48500 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an

output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge,

falling edge, active-low, or active-high.

F 4.2.5 PLL-based Clock Generator

N The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to

clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can

O be output on the DAO port for driving audio converters. The CS48500 defaults to running from the

external reference frequency and is switched to use the PLL output after overlays have been loaded and

C configured, either through master boot from an external FLASH or through host control. A built-in crystal

oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable

between 1:1 (default) or 2:1.

10

©Copyright 2006 Cirrus Logic, Inc.

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