FOD2200S 查看數據表（PDF） - Fairchild Semiconductor
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FOD2200S Datasheet PDF : 11 Pages
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Electrical Characteristics (Continued)
Transfer Characteristics (TA = 0°C to +85°C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA, VEH = 2V to 20V,
VEL = 0V to 0.8V, IF(OFF) = 0mA to 0.1mA unless otherwise specified.)(1)
Symbol DC Characteristics
Test Conditions
Min. Typ.* Max. Unit
IOHH
Output Leakage Current
(VOUT > VCC)
VCC = 4.5V, IF = 5mA VO = 5.5V
VO = 20V
2.0
100
µA
2.5
500
VOL Low Level Output Voltage VCC = 4.5 V, IF = 0mA, VE = 0.4 V,
IOL = 6.4mA(2)
0.33
0.5
V
IFT Input Threshold Current
VCC = 4.5V, VO = 0.5V, VE = 0.4V,
IOL = 6.4mA
1.6
mA
VOH Logic High Output Voltage IOH = -2.6mA
2.4 VCC – 1.8
V
IOZL High Impedance State
Output Current
VO = 0.4V, VEN = 2V, IF = 5mA
-20
µA
IOZH
High Impedance State
Output Current
VO = 2.4 V, VEN = 2 V, IF = 5mA
VO = 5.5 V, VEN = 2 V, IF = 5mA
20
µA
100
VO = 20 V, VEN = 2 V, IF = 5mA
500
IOSL Logic Low Short Circuit
VO = VCC = 5.5V, IF = 0mA
25
mA
Output Current(10)
VO = VCC = 20V, IF = 0mA
40
IOSH Logic High Short Circuit
VCC = 5.5V, IF = 5mA, VO = GND
-10
mA
Output Current(10)
VCC = 20V, IF = 5mA, VO = GND
-25
IHYS Input Current Hysteresis VCC = 4.5V
0.03
mA
Isolation Characteristics (TA = 0°C to +85°C unless otherwise specified)
Symbol
Characteristics
VISO
RI-O
CI-O
Withstand Insulation Test Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
Test Conditions
RH < 50%, TA = 25°C, t = 1 min.(9)
VI-O = 500 VDC(9)
VI-O = 0V, f = 1MHz(9)
Min.
5000
Typ.*
1012
0.6
Max.
Unit
VRMS
Ω
pF
*Typical values at TA = 25°C, VCC = 5V, IF(ON) = 3mA unless otherwise stated.
Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. tPLH – Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse
to the 1.3V level on the LOW to HIGH transition of the output voltage pulse.
3. tPHL – Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse
to the 1.3V level on the HIGH to LOW transition of the output voltage pulse.
4. When the peaking capacitor is omitted, propagation delay times may increase by 100ns.
5. tr – Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.
6. tf – Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.
7. CMH – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high
state (i.e., VOUT > 2.0V).
8. CML – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low
state (i.e., VOUT < 0.8V).
9. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted together.
10. Duration of output short circuit time should not exceed 10ms.
©2004 Fairchild Semiconductor Corporation
FOD2200 Rev. 1.0.1
4
www.fairchildsemi.com
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