IA6805E2-PDW40I-00 查看數據表（PDF） - InnovASIC, Inc
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IA6805E2-PDW40I-00 Datasheet PDF : 33 Pages
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IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
I/O Pin Functions
R/W-n DDR
I/O Pin Functions
0
0 The I/O pin is in input mode. Data is
written into the output data latch.
0
1 Data is written into the output data latch and
output to the I/O pin.
1
0 The state of the I/O pin is read.
1
1 the I/O pin is in an output mode. The
output data latch is read.
I/O Port Circuitry and Register Configuration:
DATA DIRECTION
REGISTER
BIT
TO
AND
LATCHED
OUTPUT
FROM
DATA BIT
OUTPUT
I/O
PIN
CPU
INPUT
REG
BIT
INPUT
I/O
PIN
76543210
DATA DIRECTION
A(B)
REGISTER
DDA7
(DDB7)
DDA6 DDA5
(DDB6) (DDB5)
DDA4
(DDB4)
DDA3
(DDB3)
DDA2 DDA1
(DDB2) (DDB1)
DDA0
(DDB0)
$0004 ($0005)
PORT A(B)
REGISTER
$0000 ($0001)
PIN
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
(PB7) (PB6) (PB5) (PB4) (PB3) (PB2) (PB1) (PB0)
Figure 2. PA0-PA7/PB0-PB7 (Input/Output Lines)
Copyright © 2007
©
IA211081401-03
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