INDT165B 查看數據表（PDF） - Unspecified

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INDT165B

Long Distance Digital Display Link Transmitter & Receiver

Unspecified 

Data Sheet

INDT/R165B

INDT/R330B

2 Device Configuration

The GigaSTaR Digital Display Link allows for configuring the pixel-, sideband- and audio-interface. To configure the

devices, four configuration vectors (cfg0 – cfg3, 4-bit each) must be loaded into the device through the low-speed sideband

data interfaces SB0 and SB2. The Tx and the Rx device must be connected via the downlink.

2.1 Configuration Vectors and Configuration Data

SB0 and SB2 sideband data are multiplexed and are also used for device configuration. After de-assertion of RESET#,

CFG_CYC is automatically being driven high and enables the configuration process.

The configuration select signals (CFG_SEL[3:0]) are provided sequentially at SB0 (INDT) respectively at SB2 (INDR).

These select signals enable e.g. an external logic which provides the configuration vectors (cfg0 – cfg3) via the

configuration signals CFG_D[3:0]. These are read at SB2 (INDT) respectively at SB0 (INDR).

Sequence

1

2

3

4

Vector

name

cfg0

cfg1

cfg2

cfg3

Configuration Select Signals

CFG_SEL[3:0]

0001

0010

0100

1000

Configuration vector

Requests configuration vector 0

Requests configuration vector 1

Requests configuration vector 2

Requests configuration vector 3

Table 2.1: Configuration Vector Sequence

Configuration mode

(CFG_CYC = 1)

Transmitter

CFG_SEL[3:0]

CFG_D[3:0]

Receiver

CFG_SEL[3:0]

CFG_D[3:0]

Normal mode

(CFG_CYC = 0)

SB0_D[3:0]

SB2_D[3:0]

SB2_D[3:0]

SB0_D[3:0]

Table 2.2: Pin Naming Multiplex Matrix

CFGEN

SYNC1/0

SB0_D[3…0]

SB1_D[1…0]

SDB

CFGDATA

LOW

LOW

t>1ms

t>1ms

For proper initialization of the upstream channel the side band data input at the Rx needs to be kept low for >1ms after the

SYNC1/0 went high.

Date: 2005-02-18 Revision: 1.1

Page 12 of 41

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