IND330SK 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

IND330SK

Long Distance Digital Display Link Transmitter & Receiver

Unspecified 

Data Sheet

INDT/R165B

INDT/R330B

Mode

1

2

3

INDT/R330B configurations

High-speed

Sideband

Low-speed

Sideband

Audio

X

X

X/–

–

X

X

–

–

–

Up to

VESA-Mode

SXGA 24 color bits

UXGA 18 color bits

UXGA 18 color bits

Table 1.2: INDT/R330B Video Configuration

Note: Implementation of video modes other than VESA is possible. Special modes may need evaluation.

1.2 Pixel Interface

1.2.1 General Information

The pixel interface is designed to support direct interfacing to any digital graphics device with a parallel data port such as

graphic-cards/controllers, CCD cameras or flat panel TFT displays. With standard interface devices the data port can also

be adapted to systems with non-generic parallel interfaces such as DVI or LVDS/OpenLDI.

PX_CLK+

PX_CLK–

PX_D[47:0]

48

PX_HSYNC

PX_VSYNC

PX_DE

Video

Downstream

INDT

Transmitter

PX_CLK+

Video

48

INDR

Receiver

PX_D[47:0]

PX_HSYNC

PX_VSYNC

PX_DE

Figure 1.2: Pixel Interface

Signal

PX_D[47:0]

PX_CLK+

PX_CLK–

PX_HSYNC

PX_VSYNC

PX_DE

Tx1 Rx Description

IN OUT Configurable parallel pixel data interface

IN OUT Pixel clock 24 – 161 MHz, diff + or single-ended

IN OUT Pixel clock 24 – 161 MHz, diff –

IN OUT Pixel data framing – Horizontal sync pulse

IN OUT Pixel data framing – Vertical sync pulse

IN OUT Pixel data framing – Data enable

Table 1.3: Pixel Interface Signals

1 Configurable to 3.3V or 1.8V input levels via VREF-pin.

Date: 2005-02-18 Revision: 1.1

Page 4 of 41

Share Link: