K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Preliminary
FLASH MEMORY
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG
-
0.8
3
ms
Dummy Busy Time for Multi Plane Program
tDBSY
0.5
1
µs
Number of Partial Program Cycles in the Same Page
Nop
-
-
1
cycle
Block Erase Time
tBERS
-
1.5
10
ms
NOTE
1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2. Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature.
3. Within a same block, program time(tPROG) of page group A is faster than that of page group B. Typical tPROG is the average program time of the
page group A and B(Table 2).
Page Group A: Page 0, 1, 2, 3, 6, 7, 10, 11, ... , 110, 111, 114, 115, 118, 119, 122, 123
Page Group B: Page 4, 5, 8, 9, 12, 13, 16, 17, ... , 116, 117, 120, 121, 124, 125, 126, 127
AC Timing Characteristics for Command / Address / Data Input
Parameter
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
Address to Data Loading Time
Symbol
tCLS(1)
tCLH
tCS(1)
tCH
tWP
tALS(1)
tALH
tDS(1)
tDH
tWC
tWH
tADL(2)
Min
15
5
20
5
15
15
5
15
5
30
10
100(2)
Max
-
-
-
-
-
-
-
-
-
-
-
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12