LCMXO1200E-3M132IES 查看數據表（PDF） - Lattice Semiconductor

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LCMXO1200E-3M132IES

MachXO Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

Architecture

MachXO Family Data Sheet

There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU).

There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the sig-

nals associated with each Slice.

Figure 2-5. Slice Diagram

To Adjacent Slice/PFU

A1

B1

C1

D1

From

Routing

M1

M0

A0

B0

C0

D0

CO

F

LUT4 &

CARRY SUM

CI

Slice

D

FF/

Latch

CO

LUT

Expansion

Mux

LUT4 &

CARRY

CI

F

SUM

OFX0

D

FF/

Latch

OFX1

F1

Fast Connection

to I/O Cell*

Q1

To

Routing

OFX0

Fast Connection

to I/O Cell*

F0

Q0

Control Signals

CE

selected and

CLK

inverted per

Slice in routing

LSR

From Adjacent Slice/PFU

Notes:

Some inter-Slice signals are not shown.

* Only PFUs at the edges have fast connections to the I/O cell.

Table 2-1. Slice Signal Descriptions

Function

Type

Signal Names

Description

Input

Data signal

A0, B0, C0, D0 Inputs to LUT4

Input

Data signal

A1, B1, C1, D1 Inputs to LUT4

Input

Multi-purpose

M0/M1

Multipurpose Input

Input

Control signal

CE

Clock Enable

Input

Control signal

LSR

Local Set/Reset

Input

Control signal

CLK

System Clock

Input

Inter-PFU signal

FCIN

Fast Carry In1

Output

Data signals

F0, F1

LUT4 output register bypass signals

Output

Data signals

Q0, Q1

Register Outputs

Output

Data signals

OFX0

Output of a LUT5 MUX

Output

Data signals

OFX1

Output of a LUT6, LUT7, LUT82 MUX depending on the Slice

Output Inter-PFU signal

FCO

Fast Carry Out1

1. See Figure 2-4 for connection details.

2. Requires two PFUs.

2-4

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