White Electronic Designs
WS1M8-XXX
ADDRESS
DATA I/O
TIMING WAVEFORM – READ CYCLE
tRC
ADDRESS
tRC
tAA
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE 1 (CS# = OE# = VIL, WE# = VIH)
CS#
OE#
DATA I/O
tACS
tCLZ
tOE
tOLZ
HIGH IMPEDANCE
tCHZ
tOHZ
DATA VALID
NOTE: OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
READ CYCLE 2 (WE# = VIH)
WRITE CYCLE – WE# CONTROLLED
ADDRESS
CS#
WE#
DATA I/O
tWC
tAW
tAH
tCW
tAS
tWP
tWHZ
tOW
tDW
tDH
DATA VALID
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE – CS# CONTROLLED
ADDRESS
CS#
WE#
DATA I/O
tWC
tAW
tAS
tCW
tAH
tWP
tDW
tDH
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com