MAX5820 查看數據表（PDF） - Maxim Integrated

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MAX5820

Dual, 8-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC

Maxim Integrated 

Dual, 8-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

S

SCL

SDA

Sr

P

Figure 2. START and STOP Conditions

SCL

SDA

STOP

START

LEGAL STOP CONDITION

SCL

SDA

START

ILLEGAL

STOP

ILLEGAL EARLY STOP CONDITION

Figure 3. Early STOP Conditions

Acknowledge Bit (ACK)

The acknowledge bit (ACK) is the ninth bit attached to

any 8-bit data word. ACK is always generated by the

receiving device. The MAX5820 generates an ACK

when receiving an address or data by pulling SDA low

during the ninth clock period. When transmitting data,

the MAX5820 waits for the receiving device to generate

an ACK. Monitoring ACK allows for detection of unsuc-

cessful data transfers. An unsuccessful data transfer

occurs if a receiving device is busy or if a system fault

has occurred. In the event of an unsuccessful data

transfer, the bus master should reattempt communica-

tion at a later time.

Slave Address

A bus master initiates communication with a slave

device by issuing a START condition followed by the 7-

bit slave address (Figure 4). When idle, the MAX5820

waits for a START condition followed by its slave

address. The serial interface compares each address

value bit-by-bit, allowing the interface to power down

immediately if an incorrect address is detected. The

LSB of the address word is the Read/Write (R/W) bit.

R/W indicates whether the master is writing to or read-

ing from the MAX5820 (R/W = 0 selects the write condi-

tion, R/W = 1 selects the read condition). After

receiving the proper address, the MAX5820 issues an

ACK by pulling SDA low for one clock cycle.

The MAX5820 has four different factory/user-pro-

grammed addresses (Table 2). Address bits A6

through A1 are preset, while A0 is controlled by ADD.

Connecting ADD to GND sets A0 = 0. Connecting ADD

to VDD sets A0 = 1. This feature allows up to four

MAX5820s to share the same bus.

Table 2. MAX5820 I2C Slave Addresses

PART

MAX5820L

MAX5820L

MAX5820M

MAX5820M

VADD

GND

VDD

GND

VDD

DEVICE ADDRESS

(A6–A0)

0111 000

0111 001

1011 000

1011 001

Write Data Format

In write mode (R/W = 0), data that follows the address

byte controls the MAX5820 (Figure 5). Bits C3–C0 con-

figure the MAX5820 (Table 3). Bits D7–D0 are DAC

data. Bits S3–S0 are sub-bits and are always 0. Input

and DAC registers update on the falling edge of SCL

during the acknowledge bit. Should the write cycle be

prematurely aborted, data is not updated and the write

cycle must be repeated. Figure 6 shows two example-

write data sequences.

Extended Command Mode

The MAX5820 features an extended command mode

that is accessed by setting C3–C0 = 1 and D7–D4 = 0.

S A6 A5 A4 A3 A2 A1 A0 R/W

Figure 4. Slave-Address Byte Definition

C3 C2 C1 C0 D7 D6 D5 D4

Figure 5. Command-Byte Definition

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