MAX6746 查看數據表（PDF） - Maxim Integrated
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MAX6746 Datasheet PDF : 14 Pages
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µP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Interfacing to Other Voltages for
Logic Compatibility
The open-drain RESET output can be used to interface
to a µP with other logic levels. As shown in Figure 6, the
open-drain output can be connected to voltages from 0
to 6V.
Generally, the pullup resistor connected to the RESET
connects to the supply voltage that is being monitored
at the IC’s VCC pin. However, some systems can use
the open-drain output to level-shift from the monitored
supply to reset circuitry powered by some other supply.
Keep in mind that as the supervisor’s VCC decreases
towards 1V, so does the IC’s ability to sink current at
RESET. Also, with any pullup resistor, RESET is pulled
high as VCC decays toward zero. The voltage where
this occurs depends on the pullup resistor value and
the voltage to which it is connected.
Ensuring a Valid RESET Down to VCC = 0V
(Push-Pull RESET)
When VCC falls below 1V, RESET current sinking capabil-
ities decline drastically. The high-impedance CMOS-
logic inputs connected to RESET can drift to undeter-
mined voltages. This presents no problems in most
applications, since most µPs and other circuitry do not
operate with VCC below 1V.
In those applications where RESET must be valid down
to 0V, add a pulldown resistor between RESET and
GND for the MAX6746/MAX6748/MAX6750/MAX6752
push/pull outputs. The resistor sinks any stray leakage
currents, holding RESET low (Figure 7). The value of the
pulldown resistor is not critical; 100kΩ is large enough
not to load RESET and small enough to pull RESET to
ground. The external pulldown can not be used with
the open-drain reset outputs.
VCC
VCC
MAX6746
MAX6748
MAX6450
MAX6752
RESET
GND
100kΩ
Figure 7. Ensuring RESET Valid to VCC = 0
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