MAX6746 查看數據表（PDF） - Maxim Integrated

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MAX6746

µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay

Maxim Integrated 

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

tWD1 (MIN) tWD1 (MAX) tWD2 (MIN) tWD2 (MAX)

GUARANTEED

TO ASSERT

RESET

WDI CONDITION 1

WDI CONDITION 2

GUARANTEED TO

NOT ASSERT

GUARANTEED TO

ASSERT

RESET

RESET

*UNDETERMINED

*UNDETERMINED

FAST FAULT

NORMAL OPERATION

WDI CONDITION 3

SLOW FAULT

*UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION

Figure 1. MAX6752/MAX6753 Detailed Watchdog Input Timing Relationship

Detailed Description

The MAX6746–MAX6753 assert a reset signal whenever

the VCC supply voltage or RESET IN falls below its reset

threshold. The reset output remains asserted for the

reset timeout period after VCC and RESET IN rise above

its respective reset threshold. A watchdog timer triggers

a reset pulse whenever a watchdog fault occurs.

The reset and watchdog delays are adjustable with

external capacitors. The MAX6746–MAX6751 contain a

watchdog select input that extends the watchdog time-

out period to 128x.

The MAX6752 and MAX6753 have a sophisticated

watchdog timer that detects when the processor is run-

ning outside an expected window of operation. The

watchdog signals a fault when the input pulses arrive too

early (faster that the selected tWD1 timeout period) or too

late (slower than the selected tWD2 timeout period) (see

Figure 1).

RESET is guaranteed to be in the correct logic state for

VCC greater than 1V. For applications requiring valid

reset logic when VCC is less than 1V, see the section

Ensuring a Valid RESET Output Down to VCC = 0V.

RESET IN Threshold

The MAX6748–MAX6751 monitor the voltage on RESET IN

using an adjustable reset threshold (VRESET IN) set with

an external resistor voltage-divider (Figure 2). Use the

following formula to calculate the externally monitored

voltage (VMON_TH):

VMON_TH = VRESET IN x (R1 + R2) / R2

VMON_TH

R1

VCC

Reset Output

The reset output is typically connected to the reset input

of a µP. A µP’s reset input starts or restarts the µP in a

known state. The MAX6746–MAX6753 µP supervisory

circuits provide the reset logic to prevent code-execu-

tion errors during power-up, power-down, and

brownout conditions (see theTypical Operating Circuit).

RESET changes from high to low whenever the moni-

tored voltage, RESET IN and/or VCC drop below the

reset threshold voltages. Once VRESET IN and/or VCC

exceeds its respective reset threshold voltage(s),

RESET remains low for the reset timeout period, then

goes high.

VCC

RESET IN

R2

MAX6748

MAX6749

MAX6750

GND MAX6751

VMON_TH = 1.235 x (R1 + R2) / R2

Figure 2. Calculating the Monitored Threshold Voltage

(VMON_TH)

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