MN838850 查看數據表（PDF） - Panasonic Corporation

零件编号

产品描述 (功能)

生产厂家

MN838850

Source Driver for LCD Panel Drive

Panasonic Corporation 

Color TFT LCD Driver

MN838850

s Functional Description (continued)

• Possible periods of the clock stop

The possible periods of the clock stop in which clock has been stopped are shown below.

The clock signal must be provided during the period starting one clock cycle before the start pulse input and ending 5

clock cycles after the rise of the A signal.

However, if it is not the case that the first data is input with the next clock timing (T) after the input of the start pulse,

the clock may be stopped during the period between the start pulse input and the start of data input. The clock signal

may be stopped at either the high or low level.

FY

T

Start pulse

PLSR(RL = "H")

PRSL(RL = "L")

First data

DXX

A signal

1 3 ··· N

Last data

12345

Period during which clock input is required

Period during

which clock input

may be stopped

s Electrical Characteristics

1. Absolute Maximum Ratings at AVSS = 0 V, DVSS = 0 V

Parameter

Symbol

Rating

Unit

Digital system supply voltage

DVDD

− 0.3 to +7.0

V

Analog system supply voltage AVDD

− 0.3 to +17

V

Digital input voltage

VI1

− 0.3 to DVDD+0.3

V

Analog input voltage

VI2

− 0.3 to AVDD+0.3

V

Digital output voltage

VO1

− 0.3 to DVDD+0.3

V

Analog output voltage

VO2

− 0.3 to AVDD+0.3

V

Operating temperature

Topr

−20 to +75

°C

Storage temperature

Tstg

−40 to +110

°C

Note) The absolute maximum ratings are limiting values under which the device will not be destroyed. Operation is not

guaranteed within these ranges.

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