MN8390-C 查看數據表（PDF） - Panasonic Corporation

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MN8390-C

LCD Panel Source Driver

Panasonic Corporation 

For Information Equipment

Pin Descriptions

Pin No. Symbol

99 to 102 STHR

21 to 24

STHL

Pin Name

Shift data I/O

27 to 30

RL

Shift direction

control

42 to 45

37 to 40

32 to 35

CLK1 to 3

Clock input

70 to 73

OE

Output enable

47 to 50

D1

Analog signal

swiching

MN8390-C

I/O

Function Description

I/O These are I/O pins for the bidirectional shift register.

The RL pin controls their I/O directions.

RL

STHR

H

Input

L

Output

STHL

Output

Input

(1) Input

The pins provide input data to the shift register's first

stage. The shift register reads in this data at the rising

edge of the CLK1 signal.

(2) Output

In a cascade connection, the pins provide the data for

the synchronizing output stage synchronized with the

rising edge of the CLK1 signal.

I

This pin controls the shift direction for the

bidirectional shift register.

RL="H" : QA1→ QB1→ QC1→ → QC80

RL="L" : QC80→ QB80→ QA80→ → QA1

I

These pins provide the shift clock signals that the

sample-and-hold circuits use to generate the data for

the LCD drive output pins (QA1-QC80).

The following lists the relationships between these

clock signals and the output pins.

CLK1 RL="H": QA1 to QA80

RL="L": QC1 to QC80

CLK2:

QB1 to QB80

CLK3 RL="H": QC1 to QC80

RL="L": QA1 to QA80

I

At each rising edge of this signal, the MN8390-C

switches between its two sample-and-hold circuits

and initiates output of new data. When the outputs

reach the drive potential, the MN8390-C

automatically reduces the drive power, but maintains

the outputs at the drive potential.

I

This pin controls the mapping between the three

analog inputs (VA, VB, and VC) and the drive

outputs (QA, QB, and QC).

D1

Input

Output

VA

QA1 to QA80

L

VB

QB1 to QB80

VC

QC1 to QC80

VA

QB1 to QB80

H

VB

QC1 to QC80

VC

QA1 to QA80

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