PI74ALVCHR162524A 查看數據表（PDF） - Pericom Semiconductor
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PI74ALVCHR162524A Datasheet PDF : 7 Pages
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PI74ALVCHR162524
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Product Pin Description
Pin Name
CLKEN
SEL
CLK
Ax
Bx
GND
VCC
Description
Clock Enable Input (Active LOW)
Select (Active LOW)
Clock Input (Active HIGH)
Data I/O
Data I/O
Ground
Power
Product Pin Configuration
GND
OEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
CLKENBA
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11 56-Pin 46
12 A, V 45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
SEL
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLK
GND
Truth Table(1) B to A Storage (OEBA = L)
Inputs
CLKENBA CLK SEL
B
Outputs
A
H
X
X
X
A0
L
↑
H
L
L
L
↑
H
H
H
L
↑
L
L
L§
L
↑
L
H
H§
Note:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
Output level before the indicated steady-state input
conditions were established.
§ Four positive CLK edges are needed to propagate
data from B to A when SEL is low.
2
PS8314B 11/06/00
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