74ALVC16835 查看數據表（PDF） - Philips Electronics

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74ALVC16835

18-bit universal bus driver with 5V tolerant inputs (3-State)

Philips Electronics 

Philips Semiconductors

18-bit universal bus driver with 5V tolerant inputs

(3-State)

Product specification

74ALVC16835

FEATURES

• Wide supply voltage range of 1.2V to 3.6V

• Complies with JEDEC standard no. 8-1A.

• CMOS low power consumption

• Direct interface with TTL levels

• Current drive ± 24 mA at 3.0 V

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins for minimum noise

and ground bounce

• Output drive capability 50Ω transmission lines @ 85°C

DESCRIPTION

The 74ALVC16835 is a 18–bit universal bus driver. Data flow is

controlled by output enable (OE), latch enable (LE) and clock inputs

(CP).

When LE is HIGH, the A to Y data flow is transparent. When LE is

LOW and CP is held at LOW or HIGH, the data is latched; on the

LOW to HIGH transient of CP the A–data is stored in the

latch/flip-flop.

When OE is LOW the outputs are active. When OE is HIGH, the

outputs go to the high impedance OFF–state. Operation of the OE

input does not affect the state of the latch/flip-flop.

To ensure the high-impedance state during power up or power

down, OE should be tied to VCC through a pullup resistor; the

minimum value of the resistor is determined by the current-sinking

capability of the driver.

PIN CONFIGURATION

NC 1

NC 2

Y0 3

GND 4

Y1 5

Y2 6

VCC 7

Y3 8

Y4 9

Y5 10

GND 11

Y6 12

Y7 13

Y8 14

Y9 15

Y10 16

Y11 17

GND 18

Y12 19

Y13 20

Y14 21

VCC 22

Y15 23

Y16 24

GND 25

Y17 26

OE 27

LE 28

56 GND

55 NC

54 A0

53 GND

52 A1

51 A2

50 VCC

49 A3

48 A4

47 A5

46 GND

45 A6

44 A7

43 A8

42 A9

41 A10

40 A11

39 GND

38 A12

37 A13

36 A14

35 VCC

34 A15

33 A16

32 GND

31 A17

30 CP

29 GND

SH00130

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

Propagation delay

tPHL/tPLH

An to Yn;

LE to Yn;

VCC = 3.3V, CL = 50pF

2.3

2.6

CP to Yn

2.5

Fmax

CI

CI/O

CPD

Maximum clock frequency

Input capacitance

Input/Output capacitance

VCC = 3.3V, CL = 50pF

Power dissipation capacitance per buffer

VI = GND to VCC1

350

4.0

8.0

transparent mode

Output enabled

13

Output disabled

3

Clocked mode

Output enabled

22

Output disabled

15

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.

UNIT

ns

MHz

pF

pF

pF

1999 Mar 18

2

853-2095 21052

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