R2S15901SP 查看數據表（PDF） - Renesas Electronics

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R2S15901SP

Digital Delay IC for “Lip Sync”

Renesas Electronics 

R2S15901SP

Pin Configuration

SDI

1

LRI

2

BCKI

3

VSS

4

8

VDD

7

SDO

6

COUNT1

5

COUNT0

Pin Description

Pin No. Pin Name I/O

Description

1

SDI

I

• Serial audio data input

• The input audio data are fetched at every LRI edge.

2

LRI

I

• LR clock

• Audio sample frequency.

• Low indicates the audio input data SDI and output data SDO are left channel data.

• High indicates the audio input data SDI and output data SDO are right channel data.

3

BCKI

I

• Bit clock input

• BCK clock is 64 times as large as LRI and input audio data.

4

VSS

— • Ground

5

COUNT0 I

• Delay time control 0

6

COUNT1

• Delay time control 1

• Delay time control pin. These two inputs are 3-state input pins that may be set high

or low, or left unconnected to generate the third state. With the 3-state condition, 9-

step delay time may be organized.

7

SDO

O • Audio data output

• This SDO is the delayed audio data output.

8

VDD

— • Power supply +2.5V

Rev.1.0 Apr 28, 2005 page 3 of 7

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