SI3226-X-FQ 查看數據表（PDF） - Silicon Laboratories

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SI3226-X-FQ

DUAL PROSLIC® WITH DC-DC CONTROLLER

Silicon Laboratories 

Si3226/7

Si3208/9

Table 10. Switching Characteristics—SPI

(VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)

Parameter

Symbol Test Conditions

Min

Typ

Max Unit

Cycle Time SCLK

tc

62

—

—

ns

Rise Time, SCLK

tr

—

—

25

ns

Fall Time, SCLK

tf

—

—

25

ns

Delay Time, SCLK Fall to SDO Active

td1

—

—

20

ns

Delay Time, SCLK Fall to SDO

td2

Transition

—

—

20

ns

Delay Time, CS Rise to SDO Tri-state

td3

—

—

20

ns

Setup Time, CS to SCLK Fall

tsu1

25

—

—

ns

Hold Time, CS to SCLK Rise

th1

20

—

—

ns

Setup Time, SDI to SCLK Rise

tsu2

25

—

—

ns

Hold Time, SDI to SCLK Rise

th2

20

—

—

ns

Delay Time between Chip Selects

tcs

220

—

—

ns

SDI to SDITHRU Propagation Delay

td4

—

4

10

ns

Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V

SCLK

CS

SDI

SDO

SDITHRU

tr

tc

tsu1

td1

tsu2

th2

td2

td4

Figure 1. SPI Timing Diagram

tf

th1

tcs

td3

Preliminary Rev. 0.33

11

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