SI3208 查看數據表（PDF） - Silicon Laboratories

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SI3208

DUAL PROSLIC® WITH DC-DC CONTROLLER

Silicon Laboratories 

Si3226/7

Si3208/9

Table 11. Switching Characteristics—PCM Highway Interface

(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL = 20 pF)

Parameter

Symbol

Test

Conditions

Min1

Typ1

Max1 Units

PCLK Period

tp

122

—

3906

Valid PCLK Inputs

—

512

—

—

768

—

—

1.024

—

—

1.536

—

—

1.544

—

—

2.048

—

—

4.096

—

—

8.192

—

FSYNC Period2

tfs

—

125

—

PCLK Duty Cycle Tolerance

tdty

40

50

60

FSYNC Jitter Tolerance

tjitter

—

—

±120

Rise Time, PCLK

tr

—

—

25

Fall Time, PCLK

tf

—

—

25

Delay Time, PCLK Rise to DTX Active

td1

—

—

20

Delay Time, PCLK Rise to DTX

td2

Transition

—

—

20

Delay Time, PCLK Rise to DTX

td3

Tristate3

—

—

20

Setup Time, FSYNC to PCLK Fall

tsu1

25

—

—

Hold Time, FSYNC to PCLK Fall

th1

20

—

—

Setup Time, DRX to PCLK Fall

tsu2

25

—

—

Hold Time, DRX to PCLK Fall

th2

20

—

—

FSYNC Pulse Width

twfs

tp

—

125 µs–tp

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O – 0.4 V, VIL = 0.4 V.

2. FSYNC source is assumed to be 8 kHz under all operating conditions.

3. Spec applies to PCLK fall to DTX tristate when that mode is selected.

ns

kHz

kHz

MHz

MHz

MHz

MHz

MHz

MHz

µs

%

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

12

Preliminary Rev. 0.33

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