SI3208 查看數據表（PDF） - Silicon Laboratories

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SI3208

DUAL PROSLIC® WITH DC-DC CONTROLLER

Silicon Laboratories 

Si3226/7

Si3208/9

PCLK

tsu1

FSYNC

tp

tr

th1

tfs

tsu2 th2

tf

twfs

DRX

td1

td2

td3

DTX

Figure 2. PCM Highway Interface Timing Diagram

Table 12. Switching Characteristics—GCI Highway Serial Interface

(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)

Parameter1

Symbol

Test

Min Typ Max Units

Conditions

PCLK Period (2.048 MHz PCLK Mode)

tp

—

488

—

ns

PCLK Period (4.096 MHz PCLK Mode)

tp

FSYNC Period2

tfs

—

244

—

ns

—

125

—

µs

PCLK Duty Cycle Tolerance

tdty

40

50

60

%

FSYNC Jitter Tolerance

tjitter

—

— ±120 ns

Rise Time, PCLK

tr

—

—

25

ns

Fall Time, PCLK

tf

—

—

25

ns

Delay Time, PCLK Rise to DTX Active

td1

—

—

20

ns

Delay Time, PCLK Rise to DTX Transition

td2

Delay Time, PCLK Rise to DTX Tristate3

td3

—

—

20

ns

—

—

20

ns

Setup Time, FSYNC Rise to PCLK Fall

tsu1

25

—

—

ns

Hold Time, PCLK Fall to FSYNC Fall

th1

20

—

—

ns

Setup Time, DRX Transition to PCLK Fall

tsu2

25

—

—

ns

Hold Time, PCLK Falling to DRX Transition

th2

20

—

—

ns

FSYNC Pulse Width

twfs

tp/2

—

—

ns

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V and VIL = 0.4 V.

Rise and fall times are referenced to the 20% and 80% levels of the waveform.

2. FSYNC source is assumed to be 8 kHz under all operating conditions.

3. Specification applies to PCLK fall to DTX tristate when that mode is selected.

Preliminary Rev. 0.33

13

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