SPHE8281D 查看數據表（PDF） - Unspecified
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SPHE8281D Datasheet PDF : 35 Pages
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Preliminary
SPHE8281D/Dx
Symbol
M_DQM3/GPIO
M_DQM2/GPIO
VDD_K4
R_OE_B
R_D7
R_D6
R_D5
R_D4
R_D3
VSS_O5/ VSS_K5
Pin No. I/O
141
I/O
142
I/O
143
S
144
I/O
145
I/O
146
I/O
147
I/O
148
I/O
149
I/O
150
S
Description
SDRAM data input/output mask for M_DD[31:24] , or GPIO[38]
Priority selection
Function
dir
sft_cfg0[5]=1’b1
SDRAM data
O
input/output mask for
M_DD[31:24]
(default)
sft_cfg2[3:2]=2’b11
UA0_RXD
I
sft_cfg1[8:6]=3’b011
R_CSALL_B
O
sft_cfg3[13:12]=2’b10
TV_HSYNC
I/O
sft_cfg4[15:13]=3’b010
TV_HSYNC_PC
O
sft_cfg7[7:6]=2’b01
PCMCIA_IOW _B
O
sft_cfg0[13:12]=2’b01
TV_LCD_G[2]
O
sft_cfg7[1]= 1’b0,
FM_GPIOB[19]
I/O
sft_cfg0[11]= 1’b 0,
fm_gpio_len[3:0]>9
sft_cfg8[8]=1’b1
sft_cfg8[9]=1’b1
sft_cfg8[10]=1’b1
ADC_MONO_D_L[5]
O
DAC_OPA[1]
I
OGT_BIST_FAIL
O
(other)
GPIO[38]
I/O
SDRAM data input/output mask for M_DD[23:16] , or GPIO[39]
Priority selection
Function
dir
sft_cfg0[4]=1’b1
SDRAM data
O
input/output mask for
M_DD[23:16]
(default)
sft_cfg2[3:2]=2’b11
UA0_TXD
O
sft_cfg3[13:12]=2’b10
TV_VSYNC
I/O
sft_cfg4[15:13]=3’b010
TV_VSYNC_PC
O
sft_cfg7[7:6]=2’b01
PCMCIA_IOR_B
O
sft_cfg0[13:12]=2’b01
TV_LCD_G[3]
O
sft_cfg7[1]= 1’b 0,
FM_GPIOB[18]
I/O
sft_cfg0[11]= 1’b 0,
fm_gpio_len[3:0]>9
sft_cfg8[8]=1’b1
sft_cfg8[9]=1’b1
sft_cfg8[10]=1’b1
ADC_MONO_D_L[6]
O
DAC_OPA[2]
I
BUF_CTRL_BIST_FAI
O
L
(other)
GPIO[39]
I/O
Kernel logic power supply #4
ROM / SRAM / flash output enable
ROM / SRAM / flash data bus bit [7]
ROM / SRAM / flash data bus bit [6]
ROM / SRAM / flash data bus bit [5]
ROM / SRAM / flash data bus bit [4]
ROM / SRAM / flash data bus bit [3]
Kernel logic / I/O power shared ground supply #5
© Sunplus Confidential
17
Contents are subject to change without Notice
MAY. 19, 2005
Preliminary Version: 0.1
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