VRS700-PLI23 查看數據表（PDF） - Unspecified
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VRS700-PLI23 Datasheet PDF : 45 Pages
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VRS700
VERSA
Datasheet Rev 1.3
Input/Output Ports
The VRS700 has 36 bi-directional lines grouped into
four 8-bit I/O ports and one 4-bit I/O port. These I/Os
can be individually configured as input or output.
Except for the P0 I/Os, which are of the open drain
type, each I/O is made of a transistor connected to
ground and a dynamic pull-up resistor made of a
combination of transistors.
Writing a 0 in a given I/O port bit register will activate
the transistor connected to ground, this will bring the
I/O to a LOW level.
Writing a 1 into a given I/O port bit register deactivates
the transistor between the pin and ground. In this case,
the pull-up resistor will bring the Pin to a HIGH level.
To use a given I/O as an input, one must write a 1 into
its associated port register bit.
By default, upon reset all the I/Os are configured as
input.
General Structure of an I/O Port
The following elements establish the link between the
core unit and the pins of the microcontroller:
• Special Function Register (same name as port)
• Output Stage Amplifier (the structure of this
element varies with its auxiliary function)
From Figure 4, one may see that the D flip-flop stores
the value received from the internal bus after receiving
a write signal from the core. Also, notice that the Q
output of the flip-flop can be linked to the internal bus
by executing a read instruction.
This is how one would read the content of the register.
It is also possible to link the value of the pin to the
internal bus. This is done by the “read pin” instruction.
In short, the user may read the value of the register or
the pin.
FIGURE 4: INTERNAL STRUCTURE OF ONE OF THE EIGHT I/O PORT LINES
Read Register
Internal Bus
Write to
Regi ster
Q
D Flip-Flop
Q
Output
Stage
IC Pin
Read Pin
Structure of the P1, P2, P3 and P4 Ports
The following figure (Figure 5) gives a general idea of
the structure of one of the lines of the P1, P2 and P3
ports. For each port, the output stage is composed of a
transistor (X1) and 3 other pull-up transistors. It is
important to note that the figure below does not show
the intermediary logic that connects the output of the
register and the output stage together because this
logic varies with the auxiliary function of each port.
FIGURE 5: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2 AND P3
Read Register
Internal Bus
Write to
Regi ster
Q
D Flip-Flop
Q
Vcc
Pull-up
Network
X1
IC Pin
Read Pin
Each line may be used independently as a logical
input or output. When used as an input, as mentioned
earlier, the corresponding bit register must be high.
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