VRS700-PLI23 查看數據表（PDF） - Unspecified
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VRS700-PLI23 Datasheet PDF : 45 Pages
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VRS700
VERSA
Datasheet Rev 1.3
Data Bank Control Register
The DBANK register allows the user to map the entire
content of the RAM memory in the 64 bytes RAM
memory window ranging from 40h to 7Fh. This allows
for faster direct addressing of the entire RAM content.
The Data Bank Control Register permits this feature to
be activated and selects which 64-byte-block of RAM
will be mapped into the 40h to 7Fh window.
The Data Bank Select function is activated by setting
the Data Bank Select enable bit (BSE) to 1. Setting this
bit to zero disables this function. The 6 least significant
bits of this register control the mapping of the entire 4K
bytes on-chip RAM space into the 040h-07Fh range.
See tables 8 and 9.
TABLE 8: DATA BANK CONTROL REGISTER (DBANK) – SFR 86H
7
6
5
4
3
2
BSE unused BS5 BS4 BS3 BS2
1
0
BS1 BS0
Bit Mnemonic Description
7
BSE
Data Bank Select Enable Bit
BSE=1, Data Bank Select enabled
BSE=0, Data Bank Select disabled
6
Unused
-
5
BS5
Allows the mapping of the 4K RAM into the
4
BS4
040h - 07Fh RAM space. See Table 8 for a
3
BS3
complete description.
2
BS2
1
BS1
0
BS0
Example: User writes #30h to 101h address:
MOV DBANK, #88H
MOV A, #30H
;Set bank mapping 40h-07Fh to
0100h-013Fh
;Store #30H to A
MOV 41H, A
;Write #30 to 0101h
;address
TABLE 9:BANK MAPPING DIRECT ADDRESSING MODE
BS5 BS4 BS3 BS2 BS1 BSO
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
040h~ 07fh
mapping
address
000h-
03Fh
040h-
07Fh
080h-
0BFh
0C0h-
0FFh
0
0
0
1
0
0
0000h-
003Fh
0
0
0
1
0
1
0040h-
007Fh
0
0
0
1
1
0
0080h-
00BFh
0
0
0
1
1
1
00C 0h-
00FFh
0
0
1
0
0
0
0100h-
013Fh
0
0
1
0
0
1
0140h-
017Fh
0
0
1
0
1
0
0180h-
01BFh
0
0
1
0
1
1
01C 0h-
01FFh
0
0
1
1
0
0
0200h-
023Fh
0
0
1
1
0
1
0240h-
027Fh
0
0
1
1
1
0
0280h-
02BFh
0
0
1
1
1
1
02C 0h-
02FFh
0
1
0
0
0
0
0300h-
033Fh
0
1
0
0
0
1
0340h-
037Fh
0
1
0
0
1
0
0380h-
03BFh
0
1
0
0
1
1
03C 0h-
03FFh
0
1
0
1
0
0
0400-
043Fh
0
1
0
1
0
1
0440h-
047Fh
0
1
0
1
1
0
0480h-
04BFh
…
(Follow the same pattern)
…
1
1
1
0
1
0
0D80h-
0DBFh
1
1
1
0
1
1
0DC0h-
0DFFh
1
1
1
1
0
0
0E00h-
0E3Fh
1
1
1
1
0
1
0E40h-
0E7Fh
1
1
1
1
1
0
0E80-
0EBFh
1
1
1
1
1
1
0EC0h-
0EFFh
Note
Lower 128
byte RAM
Lower 128
byte RAM
Upper 128
byte RAM
Upper 128
byte RAM
On-chip
expanded
768 byte
RAM
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