XRT91L81 查看數據表（PDF） - Exar Corporation
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XRT91L81 Datasheet PDF : 40 Pages
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XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PIN DESCRIPTIONS
PRELIMINARY
SERIAL MICROPROCESSOR INTERFACE
NAME
LEVEL
TYPE
PIN
Host/Hw
LVTTL
I
C9
CS
LVTTL
I
A10
SCLK
LVTTL
I
B9
SDI
LVTTL
I
A9
SDO
LVTTL
O
C8
INT
LVTTL
O
C11
Reset
LVTTL
I
B10
DESCRIPTION
Host or Hardware Mode Select Input
The XRT91L81 offers two modes of operation for interfacing to the
device. The Host mode uses a serial microprocessor interface for
programming individual registers. The Hardware mode is controlled
by the state of the hardware pins set by the user. By default, the
device is configured in the Hardware mode.
"Low" = Hardware Mode
"High" = Host Mode
Chip Select Input (Host Mode Only)
Active low signal. This signal enables the serial microprocessor
interface by pulling chip select "Low". The serial microprocessor is
disabled when the chip select signal returns "High".
Serial Clock Input (Host Mode Only)
Once CS is pulled "Low", the serial microprocessor interface
requires 16 clock cycles for a complete Read or Write operation.
Serial Data Input (Host Mode Only)
When CS is pulled "Low", the serial input data is sampled on the ris-
ing edge of SCLK.
Serial Data Output (Host Mode Only)
If a Read function is initiated, the serial output data is updated on
the falling edge of SCLK8 through SCLK15, with the LSB (D0)
updated first. This enables the data to be sampled on the rising
edge of SCLK9 through SCLK16.
Interrupt Output (Host Mode Only)
Active low signal. This signal is asserted "Low" when a change in
alarm status occurs. Once the status registers have been read, the
interrupt pin will return "High".
Master Reset Input
Active low signal. When this pin is pulled "Low" for more than 10µS,
the internal registers are set to their default state. See the register
description for the default values.
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